Packaging substrate and method of fabricating the same

A technology of packaging substrate and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the problems of unfavorable thinness of electronic products, large thickness of packaging substrate, and difficulty in miniaturization, etc., and achieve electrical signal The effect of shortening the transfer path, reducing the overall thickness, and increasing the yield

Active Publication Date: 2012-05-16
UNIMICRON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] However, the conventional packaging substrate with a single-layer circuit layer still has a carrier plate for supporting the circuit layer, so the thickness of the overall package substrate is about 130 microns, which is similar to that of a general package substrate with double-layer circuit layers. Therefore, it is not conducive to the thinning and lightening of electronic products
[0013] Therefore, how to avoid problems such as the excessive thickness of the packaging substrate in the conventional technology and the difficulty of miniaturization has become an urgent problem to be solved at present.

Method used

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  • Packaging substrate and method of fabricating the same
  • Packaging substrate and method of fabricating the same
  • Packaging substrate and method of fabricating the same

Examples

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no. 1 example

[0071] see Figure 2A to Figure 2I , which is a cross-sectional view of the first embodiment of the packaging substrate and its manufacturing method of the present invention, wherein, Figure 2G 'and Figure 2G "for Figure 2G Different implementations of the top view of , Figure 2H 'and Figure 2I ’ respectively Figure 2H and Figure 2I Another implementation method of .

[0072] like Figure 2A As shown, a metal plate 20 is provided having opposing first and second surfaces 20a, 20b.

[0073] like Figure 2B As shown, a resist layer 21 is formed on the first surface 20a, and the resist layer 21 has a plurality of resist layer openings 210 exposing the first surface 20a.

[0074] like Figure 2C As shown, the metal plate 20 not covered by the resistive layer 21 is removed to form a concave portion 200 and a plurality of metal protrusions 201 as circuit layers.

[0075] like Figure 2D As shown, the resistance layer 21 is removed, and the circuit layer (ie, the m...

no. 2 example

[0087] see Figure 3A to Figure 3D , which is a cross-sectional view of the second embodiment of the packaging substrate and its manufacturing method of the present invention, wherein, Figure 3D 'for Figure 3D Another implementation method of .

[0088] like Figure 3A shown, which is a continuation from Figure 2D , forming a dielectric layer 22 on the first surface 20 a and the concave portion 200 , and the material of the dielectric layer 22 is epoxy resin (epoxy).

[0089] like Figure 3B As shown, a plurality of openings 220 for contact pads are formed in the dielectric layer 22 to expose each of the contact pads 201 b correspondingly. The method of forming the openings 220 for contact pads can be laser ablation or exposure and development.

[0090] like Figure 3C As shown, part of the thickness of the metal plate 20 is removed to expose the metal protrusions 201 .

[0091] like Figure 3D As shown, an insulating protection layer 29 covering the metal protrusio...

no. 3 example

[0094] see Figure 4A to Figure 4D , which is a cross-sectional view of the third embodiment of the packaging substrate and its manufacturing method of the present invention, wherein, Figure 4D 'for Figure 4D Another implementation method of .

[0095] The third embodiment is substantially the same as the second embodiment, the main difference being that the material of the dielectric layer 22 in this embodiment is a solder resist material, which is different from the epoxy resin in the second embodiment.

[0096]The present invention also provides another packaging substrate, including: a dielectric layer 22, which has an opposite external surface 22a and a crystal mounting surface 22b; and a circuit layer, embedded in the dielectric layer 22, and the circuit layer has solder The finger pad 201a, the contact pad 201b, and the circuit 201c electrically connecting the solder finger pad 201a and the contact pad 201b, the circuit layer is exposed on the crystal surface 22b, a...

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Abstract

A packaging substrate and a method of fabricating the packaging substrate. The packaging substrate includes: a dielectric layer that has an external contact surface and an opposing chip mounting surface; a circuit layer that is embedded in the dielectric layer and exposed from the external contact surface and the chip mounting surface, the circuit layer having wire-bonding pads, conductive pads, and a circuit that electrically connects the wire-bonding pads and the conductive pads, wherein the widths of the wire-bonding pads, conductive pads, and the circuit narrow gradually from chip mounting surface to the external contact surface; and a first insulating protective layer disposed on the external contact surface of the dielectric layer and covering the dielectric layer and the circuit layer, a plurality of conductive pad openings being formed in the first insulating protective layer for exposing the conductive pads. The dielectric layer is used directly as a foundation of the packaging substrate, thereby providing advantage in miniaturization, simpler fabrication procedure, and thus low cost production.

Description

technical field [0001] The invention relates to a packaging substrate and a manufacturing method thereof, in particular to a packaging substrate with a single circuit layer and a manufacturing method thereof. Background technique [0002] In the packaging history of semiconductor chips, lead frame packaging substrates have been used for a long time, mainly because they have the advantages of lower manufacturing cost and higher reliability; in addition, for input / output (I / O ) for a lower number of semiconductor chips, lead frame package substrates are still very cost-competitive. [0003] In some cases, such as relatively simple or simple electronic products, the required packaging substrate only needs to have a single circuit layer. [0004] see Figure 1A to Figure 1G , which is a cross-sectional view of a conventional packaging substrate with a single circuit layer and its manufacturing method. [0005] like Figure 1A As shown, a carrier board 10 is provided, both sur...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/488H01L23/31H01L21/60H01L21/56
CPCH01L2224/48235H01L23/3121H01L24/48H01L2224/85444H01L2224/48091H01L2224/73265H01L23/49827H01L23/49861H01L2224/48227H01L2224/32225H01L24/73H01L2924/00014H01L2924/181Y10T29/49155H01L2924/00012H01L2224/45099H01L2224/45015H01L2924/207
Inventor 周保宏张宪民
Owner UNIMICRON TECH CORP
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