Method for making fully self-aligning bar gate power vertical bilateral diffusion field-effect tranisistor

Abstract

The invention relates to the technical field of semiconductor device and integrated circuit fabrication technologies and discloses a method for preparing a DMOS power transistor with a fully self aligned strip-type gate. The method comprises: A. epitaxial growth is carried out on a substrate, and a field area is oxidized thereafter, thereby forming a field oxide layer; B. the field oxide layer in active area is etched, a gate region is oxidized, then, amorphous silicon is deposited, and the deposited amorphous silicon is doped thereafter; C. lithography, etching and boron injection are carried out on the amorphous silicon after being doped, and the injected boron is pushed forward under high temperature, thereby forming a P-type well region; D. the amorphous silicon is injected with arsenic to form a shallow source region, and then a side wall is formed by deposition and anti-etching; E. boron is injected into the amorphous silicon, a cobalt film is deposited, and then cobalt silicide is formed, and P-type well contact is formed by making use of the cobalt silicide; F. boron-phosphorosilicate glass is deposited, and pulling holes are formed by lithography and etching; G. metal is deposited by sputtering, and lithography and etching are carried out thereafter. The invention simplifies the fabrication process, reduces the fabrication cost and improves the operating frequency of the DMOS power transistor.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices and integrated circuit manufacturing technology, in particular to a method for manufacturing a fully self-aligned strip gate power vertical double-diffusion field-effect transistor (VerticalDouble-diffusion MOSFET, DMOS). Background technique [0002] Power DMOS transistors have been widely used in various electronic devices. Power DMOS transistors have the characteristics of fast switching speed, high input impedance, low driving power consumption, good frequency characteristics, highly linear transconductance, etc., and have a negative temperature coefficient, no secondary breakdown problem of bipolar power transistors, and a large safe working area . Therefore, whether it is a switching application or a linear application, DMOS transistors are ideal power devices. [0003] In the traditional power DMOS transistor manufacturing process, the polysilicon boundary is used as the ali...

AI Technical Summary

Problems solved by technology

However, in order to form a good metal contact with the P-well and N+ source, two photolithography masks (P-well contact injection mask, N+ source injection mask) are usually required, and a total of 7 to 9 masks are required. , which is not conducive to the reduction of the chip area, the process is complicated, and the cost of the chip is high; at the same time, polysilicon is used as the gate interconnection, and the series resistance is large, which limits the increase of the operating frequency

Images