Memory cell having an integrated two-terminal current limiting resistor

Abstract

A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation-in-part (CIP) of U.S. patent application Ser. No. 13 / 407,359, entitled “MEMORY DEVICE HAVING AN INTEGRATED TWO-TERMINAL CURRENT LIMITING RESISTOR,” filed on Feb. 28, 2012, which is incorporated herein by reference in its entirety for all purposes.BACKGROUND[0002]1. Technical Field[0003]This disclosure relates generally to the formation of resistive switching memory cells and, more specifically, to memory cells including resistor structures.[0004]2. Description of the Related Art[0005]Nonvolatile memory devices are used in systems in which persistent storage is required. For example, nonvolatile memory cards are used in digital cameras to store images and in digital music players to store audio data. Nonvolatile memory devices are also used to persistently store data in computer environments.[0006]Electrically-erasable programmable read only memory (EEPROM) technology is often used to form and program non...

AI Technical Summary

Benefits of technology

This patent describes a memory cell with a unique resistor structure that helps to improve the performance of the memory cell. The resistor structure includes a first electrode layer, a resistor layer, and a variable resistance layer. The resistor layer is integrated into the memory cell to change its electrical characteristics. The resulting memory cell has a non-linear resistance curve that allows for a controlled saturation current to be reached at low bias voltages. This helps to prevent damage to the memory cell during programming and ensures that each memory cell minimizes leakage current. Overall, this patent provides a way to improve the reliability and performance of memory cells.

Problems solved by technology

However, as device dimensions shrink, scaling issues pose challenges for traditional nonvolatile memory technology.

Although such metal oxide (MO) films exhibit bistability, the resistance of these MO films and / or the ratio of the high-to-low resistance states is (are) often insufficient to be of practical use within nonvolatile memory.

Since the variation in the difference between the resistance states is related to the resistance of the resistive switching memory element, it is often hard to use a low resistance metal oxide film to form a reliable nonvolatile memory device.

For example, in a nonvolatile memory device having conductive lines formed of a relatively high resistance metal such as tungsten, the resistance of the conductive lines may overwhelm the memory cell if the resistance of the metal oxide-containing resistive switching element is not sufficiently high.

This may make it difficult or impossible to sense the resistance state of the bistable metal oxide resistive switching element.

Similar issues can arise from integrating a resistive switching memory element with a current steering element (typically a diode and / or resistor).

A large current flowing through the current carrying lines in a memory device (e.g., a memory array) can also undesirably alter or disturb the “logic” state of the interconnected memory cells or possibly damage portions of the adjacently connected memory cells, due to an appreciable amount of “cross-talk” between the formed memory cells.

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