Nano-wire field effect transistor, method for manufacturing the transistor, and integrated circuit including the transistor

Abstract

Provided is a method for fabricating a nano-wire field effect transistor including steps of: preparing a nano-wire field effect transistor including two columnar members made of a silicon crystal configuring a nano-wire on a substrate are arranged on a substrate in parallel and one above the other, and an SOI substrate having a (100) surface orientation; processing a silicon crystal layer configuring the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other as to face along the ridge lines of the triangular columnar members; and processing the triangular columnar member into a circular columnar member configuring a nano-wire by hydrogen-annealing or a thermal oxidation; and an integrated circuit including the transistor.

Description

TECHNICAL FIELD[0001]The present invention relates a nano-wire field effect transistor, a method for manufacturing the transistor, and an integrated circuit including the transistor.BACKGROUND ART[0002]Silicon integrated circuits have been progressed in enlarging the scale as well as in improving the performance according to so-called Moore's rule, and supported the development of the advanced information technology (IT) society from an aspect of the hardware. This trend is expected to be continued also in future. However, it is deeply concerned that miniaturization of the conventional bulk type CMOS integrated circuit will reach its limit in near future. Its main reasons are an increase in leakage current due to the miniaturization of the transistor, a degradation in switching property of the transistor (an increase in the sub-threshold slope) and so on. In other word, a serious problem lies in that the more the technology node progresses, the more percentage of inefficient power c...

AI Technical Summary

Benefits of technology

[0024]In accordance with the present invention, there are provided two nano-wires arranged one above the other on an SOI substrate having a (100) surface orientation. Therefore, the driving current of the transistor becomes twice as large as that of the conventional nano-wire field effect transistor with the same device area.

[0025]In addition, by fabricating the nano-wire with orientation dependent wet etching, the channel has a smooth surface with an atomic layer order which is superior in size reproducibility and uniformity.

[0026]Therefore, the present invention can improve a variation in size and characteristics in the conventional nano-wire having a circular cross-section shape formed by high temperature hydrogen annealing or thermal oxidizing from a nonuniform silicon thin wire prepared by RIE (Reactive Ion Etching).

Problems solved by technology

However, it is deeply concerned that miniaturization of the conventional bulk type CMOS integrated circuit will reach its limit in near future.

In other word, a serious problem lies in that the more the technology node progresses, the more percentage of inefficient power consumption due to the leakage current rather than the operating power increases.

Even with this double gate MOSFET, however, it is still not easy to perfectly suppress increase of the leakage current and the sub-threshold slope due to the short channel effect when the gate length of the device is decreased to 20 nm or below (corresponding to a stage after the 32 nm node).

Furthermore, the dimension of the channel is required to be small corresponding to shortening the gate length, but forming the small channel is difficult.

Since the threshold voltage of the FinFET described above is a fixed value, it is not available for applications such as dynamic electric power control.

When the threshold voltage is controlled by a gate voltage on one side, however, the sub-threshold slope inevitably increases significantly from the ideal value S=60 mV / decade, which leads to a degradation of the switching characteristics of the device.

Further problem is that the drain current decreases significantly when the threshold voltage is controlled by applying a voltage to one of the gate electrodes, since the gate bias works to a direction for one of the channels to close.

This structure, however, would enlarge the device area.

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