Organic thin film transistor and organic thin film transistor manufacturing process
a technology of organic thin film transistors and manufacturing processes, which is applied in the field of organic thin film transistors and organic thin film transistor manufacturing processes, can solve the problems of adversely affecting transistor performance, unable to provide source and drain electrodes with high resolution, and unable to achieve high speed and low power consumption. high, good switching property, good stability
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example 1
[0093]A layer of an aluminum-neodymium (AlNd) as an aluminum alloy was formed on a glass substrate 1 employing a sputtering method to give a thickness of 150 nm. The AlNd layer was subjected to photolithography treatment and etching treatment to form a gate electrode 2 and a contact electrode 3.
[0094]Subsequently, a SiO2 layer with a thickness of 300 nm was formed employing a plasma CVD method, whereby a gate insulating layer 4 was formed.
[0095]The surface of the resulting gate insulating layer 4 was subjected to UV ozone treatment. The resulting material was immersed in an ethanol solution containing 5 mmol of Exemplified compound (A-2) for 2 hours, and dried at 120° C. for one hour to evaporate the ethanol. The resulting material was exposed to UV light through a mask having an opening at areas where a source electrode and a drain electrode were to be formed, immersed in a Pd catalyst solution, dried, immersed in an electroless gold plating solution, and dried to form a source ele...
example 2
[0102]A glass substrate 1 subjected to a UV / ozone treatment was immersed in an-ethanol solution containing 5 mmol of Exemplified compound (A-1) for 2 hours, and dried at 120° C. for one hour to evaporate ethanol.
[0103]The resulting material was exposed to UV light through a mask having an opening at areas where a gate electrode and a contact electrode are to be formed, immersed in a Pd catalyst solution, dried, immersed in a 0.1 mol / l chromium electroless plating solution, and dried to form a gate electrode 2 and a contact electrode 3 each comprised of chromium according to the mask.
[0104]Subsequently, a SiO2 layer with a thickness of 300 nm was formed employing a plasma CVD method, whereby a gate insulating layer 4 was formed.
[0105]Subsequently, a resist pattern was provided on the insulating layer 4 according to photolithography treatment and etching treatment in order to form a source electrode and a drain electrode according to a lift-off method.
[0106]Subsequently, a chromium la...
example 3
[0113]An aluminum alloy, an aluminum-neodymium (AlNd) layer was formed on a glass substrate 1 employing a sputtering method to give a thickness-of 150 nm. The AlNd layer was subjected to photolithography treatment and etching treatment to form a gate electrode 2 and a contact electrode 3.
[0114]Subsequently, a SiO2 layer with a thickness of 300 nm was formed employing a plasma CVD method, whereby a gate insulating layer 4 was formed.
[0115]Subsequently, a resist pattern was provided on the insulating layer 4 according to photolithography treatment and etching treatment in order to form a source electrode and a drain electrode according to a lift-off method.
[0116]Subsequently, a chromium layer with a thickness of 5 nm was formed on the resist pattern in order to form a source electrode and a drain electrode, and further, a gold layer with a thickness of 50 nm was deposited on the chromium layer according to a sputtering method. Thereafter, the resist pattern was removed with a resist r...
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