Cleaning solution formulations for substrates

Abstract

A semiconductor system includes: providing a dielectric layer; providing a conductor in the dielectric layer, the conductor exposed at the top of the dielectric layer; capping the exposed conductor; and modifying the surface of the dielectric layer, modifying the surface of the dielectric layer, wherein modifying the surface includes cleaning conductor ions from the dielectric layer by dissolving the conductor in a low pH solution, dissolving the dielectric layer under the conductor ions, mechanically enhanced cleaning, or chemisorbing a hydrophobic layer on the dielectric layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This is a continuation application of U.S. patent application Ser. No. 11 / 760,722, filed Jun. 8, 2007, which claims the benefit of U.S. Provisional Patent Application Ser. No. 60 / 804,425 filed Jun. 9, 2006. The contents of U.S. patent application Ser. No. 11 / 760,722, filed Jun. 8, 2007, and the contents of U.S. Provisional Patent Application Ser. No. 60 / 804,425, filed Jun. 9, 2006, are incorporated herein, in their entirety, by this reference for all purposes.TECHNICAL FIELD[0002]The present invention relates generally to semiconductor systems, and more specifically to advanced semiconductor manufacturing systems and device systems.BACKGROUND ART[0003]Semiconductor devices are used in products as extensive as cell phones, radios, and televisions. The semiconductor devices include integrated circuits that are connected by conductive wires embedded in insulating material.[0004]With the reducing of semiconductor device size and the use of lo...

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Benefits of technology

[0025]The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.

[0015]FIG. 1 is a close up view of a semiconductor interconnect after a CMP step according to a first embodiment of the present invention;

[0016]FIG. 2 is a close up view of the semiconductor interconnect after an oxide removal step according to a first embodiment of the present invention;

[0017]FIG. 3 is a close up view of the semiconductor interconnect after a hydrophobic layer formation step according to a first embodiment of the present invention;

[0018]FIG. 4 is a close up view of the semiconductor interconnect after a capping step according to a first embodiment of the present invention;

[0019]FIG. 5 is a close up view of the semiconductor interconnect after a CMP step according to a second embodiment of the present invention;

[0020]FIG. 6 is a close up view of the semiconductor interconnect after an oxide removal step according to a second embodiment of the present invention;

[0021]FIG. 7 is a close up view of the semiconductor interconnect after a capping step according to a second embodiment of the present invention;

[0022]FIG. 8 is a close up view of the semiconductor interconnect after a post deposition treatment step according to a second embodiment of the present invention;

[0023]FIG. 9 is shown a semiconductor system used in practicing an embodiment of the present invention; and

[0024]FIG. 10 is a flow chart of a semiconductor system in accordance with another embodiment of the present invention.

[0025]The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.

[0026]In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail.

[0027]Likewise, the drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the drawing FIGS.

[0028]In addition, where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals. The embodiments have been numbered first embodiment, second embodiment, etc. as a matter of descriptive convenience and are not intended to have any other significance or provide limitations for the present invention.

[0029]For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of the integrated circuit, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” means there is direct contact among elements.

[0030]The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and / or removal of the material or as required in forming a described structure.

[0031]The term “system” as used herein means and refers to the method and to the apparatus of the present invention in accordance with the context in which the term is used.

[0032]The present invention relates to fixing dielectric induced reliability problems by minimizing or eliminating ILD contamination and surface degradation that results in higher leakage current, lower voltage breakdown and shorter time-to-dielectric breakdown.

[0033]The process flow to form a capping layer on Cu interconnects is generally made up of several steps, which may include the following:

[0034]cleaning copper surface to establish a surface free from copper oxide and strongly bound organic compounds; the same process step also serves to remove contaminants from the dielectric surface;

[0035]rinsing off the cleaning chemicals from the wafer surface;

[0036]selective deposition of metal / metal alloy cap onto copper features;

[0037]post-treatment of the metal / metal alloy cap and / or ILD to minimize deposition-induced ILD contamination and / or promote corrosion resistance of the film;

[0038]rinsing the wafer surface with deionized water; and / or

[0040]Embodiments of the present invention generally add process steps at a given point into the process flow described above.

[0041]1. Moisture removal by different drying methods after forming metal / metal alloy cap on Cu structures.

[0042]Spin rinse / dry technology that is used immediately after selectively depositing capping layer(s) on copper interconnects is not able to remove the moisture completely. A significant reduction of moisture can be achieved with one of the following processes:

[0044]i. baking in inert (N2 etc.) environment or vacuum environment or

[0046]Both of the above are performed at a temperature of about 30° C. to about 150° C.

[0047]b. critical point drying with supercritical CO2, performed after metal cap layer deposition (critical point drying uses a solution that is taken from being a subcritical fluid to supercritical fluid to avoid a gas-liquid interface by keeping the densities of the gas and liquid equivalent);

[0048]c. drying with de-hydrated agent(s) such as but not limited to dehydrated alcohol, performed after metal cap layer deposition; or

[0049]d. drying with water reactive chemicals, such as, but not limited to, di-tert-butyl dicarbonate, acetic anhydride, etc. The reactions of these compounds with water are briefly described by Eqs. 1 and 2

[0017]FIG. 3 is a close up view of the semiconductor interconnect after a hydrophobic layer formation step according to a first embodiment of the present invention;

A further advantage of these starting chemicals is that their reaction products are either gaseous or volatile compounds. This process is implemented in the final drying part of the full metal cap layer deposition process sequence. More specifically, after the metal / metal alloy cap deposition process, the wafer is generally post-cleaned by simple chemical rinse or the chemical rinse in combination with scrub then rinsed again with or without chemicals in DI, then the wafer is spin-dried to remove non-adherent water. It is after this stage when the water reactive chemical is introduced onto the wafer. After distributing the water reactive liquid on the entire wafer surface and after proper reaction time the wafer is spin-dried and the process is finished. The reaction of the water reactive liquid can be performed at room or elevated temperature to change reaction time and reaction yield.

[0051]These processes are applied as a very last step, i.e. drying, in the process flow.

[0052]2. Surface contamination removal immediately after forming metal or metal alloy cap on Cu structures:

[0053]a. by plasma (e.g. Ar, N2, NH3, H2 . . . ) clean introduced after dying step in the process flow;

[0054]b. supercritical CO2 drying as the last step in the process sequence;

[0055]c. by removing the metal ions from the dielectric surface through:

[0056]i. complexation (forming bonds in an exothermic process using chemicals such as hydroxyethylethylenediaminetetraacetic acid (HEDTA), cyanide, etc.) or

[0057]ii. altering the charge of the metal compound on ILD surface as well as the surface charge of the ILD (i.e., low pH solution (pH<2) makes both the surface as well as the metal compound positively charged; the latter is achieved by decomposing the metal compound / complex by protonating the compound that is attached to the metal ion;

[0058]d. dissolving metal if formed on the ILD in low pH solution;

[0034]cleaning copper surface to establish a surface free from copper oxide and strongly bound organic compounds; the same process step also serves to remove contaminants from the dielectric surface;

[0061]g. combination of any of the above with mechanically enhanced cleaning (e.g. scrub).

[0062]In one embodiment, the wet cleaning formulation should also contain a corrosion inhibitor and / or oxygen scavenger to minimize metal / metal alloy removal from the capping layer. In another embodiment, the wet cleaning process is performed in oxygen deprived atmosphere (O2<20% vol.).

[0063]Processes c, d, and e are also included in the post-treatment phase of the capping process.

[0064]3. Surface modification by hydrophobic layer(s). Immediately prior (on ILD) to or after (ILD, metal cap, or both) the formation of metal or metal alloy cap on Cu structures. This hydrophobic layer could either selectively chemisorb on the dielectric, on the metal / metal alloy cap or cover both metallic capping layer (like Co WP, CoWB etc.) and dielectric surface.

[0065]Such hydrophobic layers can be formed using, but not limited to, silanes containing at least one apolar group which is retained on the surface after bonding the silane through another functionality to the substrate or other inorganic anions that are attached to hydrophobic group or groups, i.e. long alkyl or aryl chains. The reactive functional groups on the silanes can be but not limited to Si—OR, Si—X or Si—NH—Si (where R is alkyl or aryl group and X is halogen).

[0069]This process creates a hydrophobic layer, so the use of any functional groups going through protonation / deprotonation reaction or hydrogen bonding in water is not recommended. Preferred water insensitive functionalities are alkyl, aryl, or their derivatives where one or more (or ultimately all) hydrogen atoms are exchanged to halogen atoms such as fluorine, chlorine, bromine, iodine with fluorine being the most preferred.

[0070]The layer can be formed by exposing the substrate to silane vapors (for the volatile silanes) or solvents, such as but not limited to ethyl alcohol, i-propanol, 1-methyl-2-pyrrolidinone or chloroform, containing the most moisture sensitive silanes or aqueous solution for less hydrolysis sensitive silanes as well as alkylphosphonates and alkylphosphates. The latter compounds, such as the less hydrolysis sensitive silanes as well as alkylphosphonates and alkylphosphates, however, can also be applied in non-aqueous solutions.

[0068]When used as prior to the capping process (i.e. prior the formation of metal or metal alloy cap on Cu structures) both the ILD as well as the embedded Cu structures has to be cleaned. The cleaning should preferably remove copper oxide from the copper structure in order to avoid silane layer formation on Cu structure. Since silane attachment to oxide-free copper is weak (if the silane compound does not contain strongly bonding groups such as amines, thiols etc.) the silane layer formation will be restricted to the dielectric area.

[0069]This process creates a hydrophobic layer, so the use of any functional groups going through protonation / deprotonation reaction or hydrogen bonding in water is not recommended. Preferred water insensitive functionalities are alkyl, aryl, or their derivatives where one or more (or ultimately all) hydrogen atoms are exchanged to halogen atoms such as fluorine, chlorine, bromine, iodine with fluorine being the most preferred.

[0070]The layer can be formed by exposing the substrate to silane vapors (for the volatile silanes) or solvents, such as but not limited to ethyl alcohol, i-propanol, 1-methyl-2-pyrrolidinone or chloroform, containing the most moisture sensitive silanes or aqueous solution for less hydrolysis sensitive silanes as well as alkylphosphonates and alkylphosphates. The latter compounds, such as the less hydrolysis sensitive silanes as well as alkylphosphonates and alkylphosphates, however, can also be applied in non-aqueous solutions.

[0071]In addition the substrate can be exposed directly to the silane compound without using any solvent if needed. The exposure is preferably performed at room temperature but lower or higher temperatures can also be used to control thickness and cross linking of the layer. Table 1 shows the results obtained with silane treatment on different type of dielectrics.

[0072]The hydrophobic layers formed from the above detailed process also act as barriers against post-process moisture uptake. Such moisture uptake for instance during storage can induce oxidation and corrosion of capping layer, which ultimately leads to higher ILD contamination and consequently higher leakage current, worse voltage breakdown, and reduced TDDB performance. In addition, the barrier performance of the capping layer against diffusion will also be adversely affected by corrosion.

[0073]The hydrophobic layer as outlined above can be formed prior to the actual capping layer deposition, right after the capping layer formation (see below) or as a part of post-treatment.

[0074]4. Surface modification by including the hydrophobic layer forming component into the deposition solution bath.

[0075]Any combination of the above mentioned methods is practical. The application is discussed with Cu interconnect as an example but not limited to Cu interconnect.

[0076]A patterned wafer is exposed to cleaning solution to remove copper oxide from the surface then rinsed and dried. Subsequently, the wafer is exposed to toluene trimethoxy silane vapor for 300 seconds at room temperature, followed by i-propanol and DI rinse. After these steps, the wafer either undergoes further cleaning step(s) or subjected to electroless deposition followed by post-clean, if needed, then rinse and dry. The surface obtained in this manner retains a strongly hydrophobic character even after the entire deposition process. In most cases, the contact angle of the surface is higher after the full process with silane treatment than the non-processed wafer. In the absence of silane treatment, the contact angle is significantly lower than that of the non-processed wafer. This statement is valid for silicon oxide or other silicon oxide containing dielectric materials such as Black Diamond.

[0077]Referring now to FIG. 1, therein is shown a close up view of a semiconductor interconnect 100 after a CMP step according to a first embodiment of the present invention.

[0078]A semiconductor wafer 102 may be of a material such as silicon, gallium arsenide, diamond, etc. The semiconductor wafer 102 has been processed to form semiconductor elements, such as transistors, in and above it.

[0079]A dielectric layer 104, such as an ILD, has been deposited on the semiconductor wafer 102. The dielectric layer 104 is of dielectric materials such as silicon oxide (SiOx), tetraethoxysilane (TEOS), borophosphosilicate (BPSG) glass, etc. with dielectric constants from 4.2 to 3.9 or low dielectric constant dielectric materials such as fluorinated tetraethoxysilane (FTEOS), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), etc. with dielectric constants below 3.9. Ultra-low dielectric constant dielectric materials are dielectric materials having dielectric constants below 2.5. Examples of such materials include commercially available Teflon, Teflon-AF, Teflon microemulsion, polimide nanofoams, silica aerogels, silica xero gels, and mesoporous silica.

[0080]The dielectric layer 104 has been processed to have a channel or via formed therein, which is lined with a barrier layer 106. The barrier layer 106 is of materials such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), tungsten (W), alloys thereof, and compounds thereof.

Problems solved by technology

With the reducing of semiconductor device size and the use of low dielectric constant (low k) interlayer dielectric (ILD) insulating materials, obtaining reliable semiconductor devices is becoming more and more challenging.

In particular, reliability problems occur at interfaces of the copper (Cu) wires and low k ILD material in the form of leakage, electromigration, stress migration, break down voltage, and time dependent dielectric breakdown (TDDB), etc.

Cu easily diffuses into silicon (Si) and causes degradation of the dielectric material.

Cu is also susceptible to oxidation and corrosion.

However, the Cu / capping layer interface is still one of the major failure paths due to the weak adhesion between Cu and the capping layer.

The mobility of these contaminants cause high leakage currents, and may cause damage to the dielectric materials when they move along the interface.

Such process is known to decrease TDDB lifetime.

While there have been many attempts to improve device reliability by applying metal / metal alloy capping layer on copper interconnect, solutions to the problems related to interface reliability problems have been long sought, but have long eluded those skilled in the art.

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