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Method for constituting graph on intermetallic dielectric layer

A technology for intermetallic dielectric layers and dielectric layers, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., and can solve problems such as increasing the dielectric constant of low dielectric layers and reducing the reliability of low dielectric layers

Inactive Publication Date: 2004-01-21
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As mentioned above, when the inner wall of the via hole is hydrophilic, the via hole absorbs a large amount of water during wet cleaning, thereby undesirably increasing the dielectric constant of the low-k layer and reducing the reliability of the low-k layer.

Method used

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  • Method for constituting graph on intermetallic dielectric layer
  • Method for constituting graph on intermetallic dielectric layer
  • Method for constituting graph on intermetallic dielectric layer

Examples

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Embodiment 1

[0023] The present invention can be better understood through the following examples, which are illustrative and should not be construed as limiting the present invention. Example 1: Comparison of the chemical composition of the inner walls of the vias before and after UV radiation

[0024] Due to the difficulty in analyzing the chemical composition constituting the inner wall of the small-sized via hole, a dielectric layer (a non-porous SiOC layer) was placed on the semiconductor substrate, and the N 2 Dry etching without a photoresist pattern was performed under an atmosphere, and then the chemical composition constituting the surface of the SiOC layer was analyzed using TOF-SIMS as the chemical composition of the via hole. The results are listed in Figure 4 . from Figure 4 It can be seen that only hydrocarbons were found after placement of the dielectric layer, but a large amount of carbonitride and nitrogen-containing amino species were found after the dry etching pr...

Embodiment 2

[0027] Example 2: Formation of via holes

[0028] A lower circuit is formed on the semiconductor substrate, and a lower etch stop layer, a lower dielectric layer, an upper etch stop layer and an upper dielectric layer are sequentially disposed on the lower circuit. At this time, non-porous silicon carbide (SiC) layers and SiOC layers are used as upper and lower etch stop layers and upper and lower dielectric layers, respectively. Then photoresist is coated on the upper and lower dielectric layers, exposed and developed to form a photoresist pattern. Use the photoresist pattern as a mask to dry etch the upper dielectric layer, the upper etch-stop layer and the lower dielectric layer in sequence to expose the lower etch stop layer 2 on the lower circuit, thereby forming a via hole in the dielectric layer .

[0029] Using a mercury lamp light source to irradiate the via hole with ultraviolet light for 60 seconds while heating at 200°C to remove the etching residue on the inner ...

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Abstract

The method for forming a pattern of the intermetal insulating film includes (a) a stage of successively forming a lower etching preventing film 2, a lower insulating film 3, an upper etching preventing film 4, and an upper insulating film 5 on a semiconductor substrate to which lower wiring 1 is formed, (b) a stage of forming a via hole to expose the lower etching preventing film by patterning the upper insulating film, the upper etching preventing film, and the lower insulating film, (c) a stage in which the vial hole is irradiated with UV light, (d) a patterning stage by forming a photo-resist film on the whole face of the semiconductor substrate in which the via hole is formed, (e) a stage of forming a wiring groove passing through the via hole on the upper insulating film by patterning the upper insulating film by making the photo-resist pattern 6 as an etching mask, and (f) a stage of exposing the upper part of the lower wiring.

Description

1. Technical field [0001] The present invention relates to a method for patterning an intermetallic dielectric layer, and more particularly, to an intermetallic dielectric that completely prevents the generation of photoresist residues on the inner wall of a via hole by irradiating ultraviolet rays after the via hole is formed. The dielectric layer constitutes a patterning method. 2. Background technology [0002] In the manufacturing process of many semiconductor devices, the demand of the dual damascene method in forming patterned metal circuits has increased, figure 1 The general method is illustrated by way of example. In this method, a double dielectric layer, that is, an upper layer and a lower layer dielectric layer, is coated on the semiconductor substrate of the exposed lower layer circuit, a via hole connecting the upper layer circuit and the lower layer circuit is formed through the lower layer dielectric layer, and the After the upper circuit pattern is formed ...

Claims

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Application Information

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IPC IPC(8): G03F7/38H01L21/3205H01L21/768
CPCH01L21/76808H01L21/76825H01L21/76814H01L21/3205
Inventor 李光熙郑铉潭李敬雨李守根
Owner SAMSUNG ELECTRONICS CO LTD
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