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Method for producing alignment mark

A technology of alignment marks and manufacturing methods, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of difficult allocation of alignment marks, neglect, and increased wafer area.

Inactive Publication Date: 2003-11-26
TAIWAN SEMICON MFG CO LTD
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Problems solved by technology

However, putting the alignment marks in the wafer will increase the area of ​​the wafer, and the alignment marks are ignored when designing the wafer layout, making it difficult to add the alignment marks after the wafer is completed
On the other hand, if the alignment mark is placed on the cutting line, the position of the alignment mark will be limited by the test line (Testline), the cursor (Vemier), the critical dimension bar (CriticalDimension Bar; CD Bar), covered Patterns, and alignment marks used in lithography, causing difficulties in dispensing alignment marks

Method used

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  • Method for producing alignment mark
  • Method for producing alignment mark
  • Method for producing alignment mark

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Embodiment Construction

[0026] From the above-mentioned known methods of manufacturing alignment marks for laser repair calibration, it can be seen that the alignment marks are made in the wafer and the area of ​​the wafer will be increased. Lines, optical scales, critical dimension bars, overlay patterns, and lithographic alignment marks overlap, so placement of the alignment marks is limited, creating dispensing headaches.

[0027] In order to reduce the wafer area and avoid the trouble caused when assigning the position of the alignment mark, the alignment mark can be made above the upper metal layer, and a dielectric layer is added between the alignment mark and the upper metal layer to prevent The occurrence of electrical short circuit. Please refer to this structure figure 2 , which is covered with a first metal layer 22 on the substrate 20 that has been formed with a plurality of semiconductor material layers, wherein the first metal layer 22 can be, for example, the upper metal layer of the...

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Abstract

During the making of alignment mark, one intermetal dielectric layer is first formed on the upper metal layer of aluminum-copper alloy, one layer of titanium nitride or other low-reflectivity material is then formed, and one metal layer is finally formed on the low-reflectivity material layer. In the metal layer, alignment mark is made, so that the alignment mark has strong contrast to the low-reflectivity material layer and thus is favorable to subsequent repair alignment. In addition, the low-reflectivity material layer may be used also as the metal layer etching stop layer.

Description

technical field [0001] The present invention relates to a method for manufacturing an alignment mark, in particular to a method for manufacturing an alignment mark on a top metal layer (Top Metal Layer). Background technique [0002] In the manufacturing process of semiconductor components, as the components become smaller and smaller, the mask pattern is also reduced. Therefore, in the Photolithography process, in order to transfer the mask pattern to the semiconductor wafer accurately, usually Several alignment marks need to be provided on the wafer for aligning the reticle so that the reticle pattern is accurately copied to the desired position on the wafer. [0003] On the other hand, in the final product testing stage, when performing laser repair (Laser Repair), in order to enable the laser to accurately cut off the unnecessary polysilicon wires (Polysilicon Fuse) in the component, it is also necessary to use alignment marks to facilitate the laser beam to be accurate....

Claims

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Application Information

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IPC IPC(8): H01L21/02
Inventor 黄俊岩李建毅傅如彬彭荣义
Owner TAIWAN SEMICON MFG CO LTD
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