Method for preparing nano CMOS parts by using side wall and solid phase diffusion of polysilicon

Abstract

The invention relates to the technique area for manufacturing very large integrated circuit, including following steps. (1) Designing the pattern of the cell. (2) Insulating components, oxidizing grids and depositing the polysilicon of the grids, before this step, the trap is made based on the need. (3) The lines of the grids are made by using the side wall translocation (4) Depositing silicon dioxide, then reactive ion etching silicon dioxide forms the side wall. Complement area of CMOS LDD is prepared by polysilicon solid diffusion. (5) Depositing silicon dioxide, reactive ion etching silicon dioxide forms, the side wall of the final components. (6) The general following up procedures form the source and the drain electrodes. Etching the contact hole, forming the metal line to connect components.

Description

Technical field: [0001] The invention relates to a method for preparing nanometer CMOS devices and circuits in the technical field of ultra-large-scale integrated circuits (ULSI), especially using sidewall transfer to realize gate lines of nanoscale MOS transistors and using heavily doped polysilicon as a solid-phase diffusion source to realize CMOS LDD regions Ultra-shallow junctions, and thus methods for the eventual realization of nanoscale CMOS devices and circuits. Background technique: [0002] As the size of the device shrinks, its characteristic physical dimensions such as channel length, PN junction depth in source and drain regions, and gate dielectric thickness are also scaled down. It is more difficult to make nanoscale gate lines and shallower LDD region PN junctions (≤50nm). , becoming the most difficult areas in the IC development process. [0003] At present, the fabrication methods of nanoscale fine grid lines mainly include traditional lithography technolo...

AI Technical Summary

Problems solved by technology

Solid phase diffusion can achieve relatively high surface impurity concentration and high impurity activation rate. The main disadvantage is that solid phase diffusion requires relatively high temperature (usually >1000°C), and the uniformity and repeatability of the process need to be improved.

PSG, BSG, etc. can only realize one kind of transistor and cannot realize CMOS at the same time, so CMOS circuits cannot be realized; the low-energy ion implantation SiO2+ solid phase diffusion process is relatively complicated, and ultra-low energy ion implantation is also required; polysilicon is widely used in MOS technology It is used as a solid-phase diffusion source for P+N junctions to realize PMOS transistors. At present, there are no reports for simultaneous realization of P+N and N+P ultra-shallow junctions.

Images