Semiconductor structure and preparation method thereof

A technology of semiconductor and wet processing, which is applied in the manufacture of semiconductor/solid-state devices, semiconductor devices, semiconductor/solid-state device components, etc. It can solve the problems of Cu metal reducing the electrical properties of devices, so as to avoid the impact of electrical properties and achieve good insulation effect of effect

Pending Publication Date: 2022-03-04
SJ SEMICON JIANGYIN CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a semiconductor structure and its preparation method, which is used to solve the problem in the prior art that the residual Cu metal after the planarization process reduces the electrical performance of the device

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  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof
  • Semiconductor structure and preparation method thereof

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Embodiment Construction

[0039] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth sho...

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Abstract

According to the semiconductor structure and the preparation method thereof provided by the invention, after planarization, the Si substrate is etched through a dry method, so that the first height difference exists between the Si substrate and the insulating layer, residual Cu metal near the edge of the Cu column can be effectively removed through wet processing, the second height difference exists between the Cu column and the insulating layer, and the first height difference is greater than the second height difference; therefore, connection of Cu metal on the inner side and the outer side of the insulating layer can be avoided, and influence on the electrical performance of the device is effectively avoided. Furthermore, through the passivation layer, the Si substrate can be effectively covered, and a conductive channel is prevented from being formed on the Si substrate in a subsequent process, so that a good insulation effect is achieved, and the influence on the electrical performance of the device can be further avoided.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, and relates to a semiconductor structure and a preparation method thereof. Background technique [0002] As the functions of integrated circuits become stronger and their performance and integration become higher and higher, packaging technology plays an increasingly important role in integrated circuit products, accounting for an increasing proportion of the value of the entire electronic system. Big. Due to the advantages of miniaturization, low cost, high integration, better performance and higher energy efficiency, wafer-level packaging (WLP) technology has become an important part of electronic equipment such as demanding mobile / wireless networks. The packaging method is one of the most promising packaging technologies at present. [0003] The redistribution layer (RDL) can re-layout the position of the pads of the chip, and arrange the new pads in an array. Therefore, the RDL is...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L23/528
CPCH01L21/76877H01L21/76883H01L23/5283
Inventor 尹佳山周祖源薛兴涛林正忠
Owner SJ SEMICON JIANGYIN CORP
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