Memory structure and manufacturing method thereof
A technology of memory and gate structure, applied in the field of semiconductor structure and its manufacturing, can solve the problem of spending a lot of energy and time
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[0042] figure 1 A top view of a memory structure according to an embodiment of the present invention. Figures 2A to 2H Manufacturing process cross-sectional view of a memory structure according to an embodiment of the present invention. image 3 for Figure 2h A peripheral circuit region and the transistor structure of a transistor array region in a schematic view. exist image 3 Omitted Figure 2h The section member to clear image 3 The positional relationship between the components.
[0043] Please refer to figure 1 and Figure 2A , Substrate 100 is provided. Substrate 100 includes a memory cell region and the peripheral circuit region R1 R2. In addition, the substrate 100 may further include a transistor array region R3. R3 transistor array region R2 is located between the memory cell region and the peripheral circuit region R1. R3 may be located in the transistor array region around the memory cell region R1. R2 may be a peripheral circuit area other than the memory cell region R1...
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