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Method for manufacturing gate oxide layer on silicon carbide material

A technology of gate oxide layer and manufacturing method, which is applied in the direction of semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of the number of trapped charges in the interface state and the reduction of oxide layer charges, and achieve the improvement of threshold voltage and channel good mobility

Inactive Publication Date: 2020-04-21
NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, this conventional manufacturing method cannot effectively reduce the number of interface state trap charges and oxide layer charges.

Method used

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  • Method for manufacturing gate oxide layer on silicon carbide material
  • Method for manufacturing gate oxide layer on silicon carbide material
  • Method for manufacturing gate oxide layer on silicon carbide material

Examples

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Embodiment 1

[0034] figure 1 It is a schematic flow chart of a method for manufacturing a gate oxide layer on a silicon carbide material provided in an embodiment of the present invention, as shown in figure 1 As shown, the present invention proposes a method for manufacturing a gate oxide layer on a silicon carbide material, comprising the following steps:

[0035] In step 101, a silicon carbide substrate is provided and placed in a low-pressure furnace tube;

[0036] Continue to set the pressure of the low-pressure furnace tube to 0.2mbar, raise the temperature inside the low-pressure furnace tube to 650°C at a rate of 5°C / min, and heat tetraethyl orthosilicate to 30°C;

[0037] In step 102, a body oxide layer with a thickness of 50 nm is deposited on the surface of tetraethyl orthosilicate silicon carbide substrate heated to 30° C. by means of low-pressure chemical vapor deposition;

[0038] In step 103, the temperature of the low-pressure furnace tube is lowered at a rate of 5°C / min ...

Embodiment 2

[0053] figure 1 It is a schematic flow chart of a method for manufacturing a gate oxide layer on a silicon carbide material provided in an embodiment of the present invention, as shown in figure 1 As shown, the present invention proposes a method for manufacturing a gate oxide layer on a silicon carbide material, comprising the following steps:

[0054] In step 101, a silicon carbide substrate is provided and placed in a low-pressure furnace tube;

[0055] Continue to set the pressure of the low-pressure furnace tube to 0.3mbar, raise the temperature inside the low-pressure furnace tube to 700°C at a rate of 10°C / min, and heat tetraethyl orthosilicate to 42°C;

[0056] In step 102, a body oxide layer with a thickness of 60 nm is deposited on the surface of tetraethyl orthosilicate silicon carbide substrate heated to 42° C. by low-pressure chemical vapor deposition;

[0057] In step 103, the temperature of the low-pressure furnace tube is lowered at a rate of 10° C. / min to 45...

Embodiment 3

[0067] figure 1 It is a schematic flow chart of a method for manufacturing a gate oxide layer on a silicon carbide material provided in an embodiment of the present invention, as shown in figure 1 As shown, the present invention proposes a method for manufacturing a gate oxide layer on a silicon carbide material, comprising the following steps:

[0068] In step 101, a silicon carbide substrate is provided and placed in a low-pressure furnace tube;

[0069] Continue to set the pressure of the low-pressure furnace tube to 0.5mbar, raise the temperature inside the low-pressure furnace tube to 750°C at a rate of 15°C / min, and heat tetraethyl orthosilicate to 50°C;

[0070] In step 102, a body oxide layer with a thickness of 70 nm is formed by depositing tetraethyl orthosilicate silicon carbide substrate surface heated to 50° C. by means of low-pressure chemical vapor deposition;

[0071] In step 103, the temperature of the low-pressure furnace tube is lowered at a rate of 15° C....

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Abstract

The invention relates to a method for manufacturing a gate oxide layer on a silicon carbide material. The method comprises the steps: depositing silicon dioxide with a thickness of 50-70 nm on a surface of silicon carbide in a low-pressure environment through a method of thermal decomposition of tetraethyl orthosilicate; carrying out first high-temperature annealing on a silicon carbide substrateon which a main body oxide layer is formed in an oxygen environment; then carrying out secondary high-temperature annealing on the oxide layer in a nitrogen atmosphere; and finally, carrying out thirdhigh-temperature treatment on the silicon carbide substrate on which the oxide layer is formed in argon. According to the manufacturing method of the gate oxide layer on the silicon carbide material,the gate oxide layer is more compact, fixed oxide layer charges and interface trapped charges formed in an oxidation process are removed, an interface state of the gate oxide layer is reduced, and performance of the gate oxide layer is improved.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a method for manufacturing a gate oxide layer on a silicon carbide material. Background technique [0002] Silicon carbide material is a third-generation wide-bandgap semiconductor material following the application of silicon and gallium arsenide. It has high thermal and chemical stability, high critical breakdown electric field strength, high carrier saturation drift velocity, and thermal conductivity. High rate. These advantages allow it to be used to manufacture various high-frequency and high-power devices suitable for extreme working environments, high temperature and radiation resistance, and used in military and civilian systems such as fighter jets, communications, automotive electronics, and space ships. Silicon carbide materials have always been highly valued by the academic community, and have become a research hotspot in the field of power electroni...

Claims

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Application Information

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IPC IPC(8): H01L21/285H01L21/28
CPCH01L21/049
Inventor 费晨曦柏松王谦张宏伟何志强刘超
Owner NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
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