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A method for preparing a multi-level fusion three-dimensional system integration structure

A system integration, multi-level technology, applied in the direction of semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of inability to complete three-dimensional integration, limited integration capabilities, and large volume

Active Publication Date: 2021-03-19
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] For high-complexity systems, due to the variety of chips and devices, the complexity of each chip and device is different, and the chips and devices come from different manufacturers, and their processes, materials, reserved connection methods and bump materials are different. At present, SOC technology cannot achieve monolithic integration of so many different chips and devices; although POP and SIP technologies can realize three-dimensional integration of the system, they are limited by process line width, pitch, layout tolerance, assembly accuracy, etc. Based on this The electronic systems of the two types of 3D integration technologies are relatively large in size, which is difficult to meet the actual needs of miniaturization; the single-layer TSV-based 3D integration technology is currently the 3D integration technology with the highest integration density. At present, the integration capability is limited, and it is impossible to complete the overall integration of such a highly complex system 3D integration

Method used

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  • A method for preparing a multi-level fusion three-dimensional system integration structure
  • A method for preparing a multi-level fusion three-dimensional system integration structure
  • A method for preparing a multi-level fusion three-dimensional system integration structure

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Embodiment 1

[0030] This embodiment provides a method for preparing a multi-level fused three-dimensional system integration structure, including the following steps:

[0031] (1) Make n substrates;

[0032] (2) Welding various electronic devices on the n substrates produced in step (1) to obtain n two-dimensional integrated packaging structures;

[0033] (3) Test n two-dimensional integrated package structures respectively;

[0034] (4) Three-dimensional integrated packaging will be performed on n two-dimensional integrated packaging structures;

[0035] (5) Capping the three-dimensional integrated packaging structure.

[0036] In the step (1), RDL layers, TSV holes, and bumps are also distributed on the n substrates.

[0037] A cavity is also provided on the substrate, so that corresponding electronic devices can be installed in the cavity.

[0038] In the step (4), the specific process of carrying out three-dimensional integrated packaging on n two-dimensional integrated packaging s...

Embodiment 2

[0043] Using the preparation method of the multi-level fusion three-dimensional system integration structure shown in Example 1 to make a four-layer fusion three-dimensional system integration structure with a basic number of four is as follows:

[0044] (1) Design and manufacture various substrates (such as silicon transfer substrates, ceramic substrates and organic substrates, etc.) according to the design requirements of the distribution, size and electrical connectivity of the bare chip PAD and bumps; Source devices (resistors and capacitors, etc.) to improve the utilization and integration of silicon interposers; design and manufacture cavities on the substrate according to the number, size, thickness and correlation between chips; design and manufacture according to interconnection requirements Redistribute RDL layers, TSVs and bumps, see figure 1 , figure 2 , image 3 ;

[0045] (2) High-precision upside-down welding of various bare chips (such as FPGA chips, CPUs w...

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Abstract

The invention relates to a preparation method of a multi-level fused three-dimensional system integrated structure. The method comprises steps of (1) manufacturing n substrates; (2) welding various electronic devices on the n substrates manufactured in the step (1) to obtain n two-dimensional integrated packaging structures; (3) respectively testing the n two-dimensional integrated packaging structures; (4) performing three-dimensional integrated packaging of the n two-dimensional integrated packaging structures; and (5) capping the three-dimensional integrated packaging structure. The preparation method of the multi-level fused three-dimensional system integrated structure is advantaged in that signal integrity of high-speed digital signal transmission and integrity of a power supply arefacilitated, and a problem that the PCB-level process technology cannot meet performance requirements of microsystems with miniaturization, high performance, low power consumption and the like is avoided.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a preparation method of a three-dimensional system integration structure with multi-level integration. Background technique [0002] With the increasing scale of system integrated chips, three-dimensional integration technology can effectively reduce the circuit board area occupied by microsystem products in the horizontal direction, and at the same time reduce the length of interconnection lines and signal delay, so that the system has a small Advantages of size, high performance, and low power consumption. [0003] For high-complexity systems, for example, if multiple chips (such as CUP, FPGA, CPLD, DSP, transceiver, A / D and power management, etc.) and devices (such as resistors, capacitors, etc.) The integration of all chips and devices can increase the interconnection density and increase the utilization rate of the circuit board area, thereby imp...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/16H01L23/538
CPCH01L23/5389H01L25/16H01L25/162H01L25/165
Inventor 单光宝杨力宏李国良朱樟明卢启军杨银堂
Owner XIDIAN UNIV
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