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A Novel Microwave 3D Integrated System-in-Package Interconnect Structure

A system-level packaging and interconnection structure technology, which is applied in the field of microwave three-dimensional integrated system-level packaging interconnection structure to achieve high processing accuracy, improve integration, and maintain signal integrity.

Active Publication Date: 2020-06-19
NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the realization of 3D integrated system-in-package interconnection of GaAs chips based on traditional technology has not been reported; therefore, it is necessary to further design a new microwave 3D integrated system-in-package interconnection technology in order to realize the existing commercial GaAs chips in Application and extension in SoP

Method used

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  • A Novel Microwave 3D Integrated System-in-Package Interconnect Structure
  • A Novel Microwave 3D Integrated System-in-Package Interconnect Structure

Examples

Experimental program
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Effect test

Embodiment 1

[0020] Such as figure 1 As shown, a microwave three-dimensional integrated system-in-package interconnection structure includes a substrate dielectric substrate 1, a microstrip line 2 on the substrate dielectric substrate, a ground metallization hole array 3 on the substrate dielectric substrate, a gallium arsenide chip 4, Silicon substrate 5, coplanar waveguide transmission line 6 on the silicon substrate, buried cavity 7 opened in the silicon substrate above the sensitive position of the gallium arsenide chip, metallized hole array ground plane metal 8 on the upper surface of the substrate medium; the sensitive position refers to part of the interior lines or active areas.

[0021] The gallium arsenide chip 4 is arranged between the silicon substrate 5 and the ground plane metal 8 , the buried cavity 7 is not penetrated above, and the microstrip line 2 is connected to the gallium arsenide chip 4 through a coplanar waveguide transmission line 6 .

Embodiment 2

[0023] The difference between this embodiment and Embodiment 1 is that a penetrating non-metallized groove is opened above the sensitive position of the gallium arsenide chip.

Embodiment 3

[0025] Such as figure 2 As shown, the difference between this embodiment and Embodiment 1 is that the interconnection structure also includes solder balls 10, through-silicon vias 11 for grounding the microstrip transmission line in the silicon substrate, and a reference ground plane 12 for the microstrip transmission line on the top surface of the silicon substrate. , the solder balls 10 are used to connect the silicon substrate 5 and the ground plane metal 8 .

[0026] The gallium arsenide chip 4 is interconnected with the microstrip transmission line 9 on the silicon substrate through flip-chip, and then the entire vertical interconnection structure is flipped onto the substrate dielectric substrate through solder balls 10, and passes through the microstrip line 2 on the substrate dielectric substrate. Interconnect with other components of the system.

[0027] The manufacturing process is as follows: Flip-chip the gallium arsenide chip 4 onto the silicon substrate 5, and ...

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Abstract

The invention discloses a novel microwave three-dimensional integrated system-level package interconnection structure, including a substrate dielectric substrate, a microstrip line arranged on the substrate dielectric substrate, a ground metallization hole array on the substrate dielectric substrate, a millimeter wave The monolithic integrated circuit and the silicon substrate; the ground plane metal is arranged on the ground metallization hole array, and the millimeter wave monolithic integrated circuit is arranged between the silicon substrate and the ground plane metal; the upper silicon substrate at the sensitive position of the millimeter wave monolithic integrated circuit is opened There is a cavity; the microstrip line is connected to the millimeter-wave monolithic integrated circuit through a planar transmission line. Compared with traditional gold wire bonding, the invention significantly reduces the interconnection size between chips, and is beneficial to maintaining the signal integrity of radio frequency and high-speed digital signal transmission.

Description

technical field [0001] The invention belongs to the technical field of electromagnetic fields and microwaves, and in particular relates to a novel microwave three-dimensional integrated system-level packaging and interconnection structure. Background technique [0002] With the continuous development of electronic information systems towards miniaturization, high performance, and multi-function, System on Package (SoP) provides a miniaturized integration solution for electronic information systems. SoP has been used in computers, mobile phones, Sensors, vehicle radar and other military and civilian fields have been widely researched and applied. However, most of the interconnections involving radio frequency chips in the current SoP are completed by gold wire bonding. The existence of gold wire is not conducive to the further integration and miniaturization of the entire system, and the gold wire interconnection at high frequency affects the work of the chip. Performance, t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01P3/08
CPCH01L23/488H01P3/081
Inventor 张君直施永荣
Owner NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD
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