Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Back side processing method of power semiconductor device

A technology of power semiconductors and processing technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as unresolved problems, and achieve increased activation rate, low conduction voltage drop, and high current-carrying area of ​​the collector area The effect of subconcentration

Inactive Publication Date: 2019-05-03
成都森未科技有限公司
View PDF10 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although the above two patents have made relevant improvements to the manufacturing method of semiconductor devices, they still have not solved the above-mentioned problems existing in the prior art

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Back side processing method of power semiconductor device
  • Back side processing method of power semiconductor device
  • Back side processing method of power semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0036] A back processing technology of a power semiconductor device comprises the steps of:

[0037] After forming a collector region and a buffer layer on the back surface of the semiconductor substrate of the first conductivity type,

[0038] The first step is to carry out the manufacturing process of the collector region of the second conductivity type, including the implantation process and the formation process. The implantation process is: the first type of ion implantation is performed from the back of the semiconductor substrate of the first conductivity type; the formation process is: performing laser annealing on the semiconductor substrate, thereby forming a first region of the second conductivity type having a higher carrier concentration than the semiconductor substrate of the first conductivity type on the back surface of the semiconductor substrate;

[0039] The second step is to perform a buffer layer manufacturing process, including an implantation process and...

Embodiment 2

[0042] A back processing technology of a power semiconductor device, comprising the steps of:

[0043] After forming a collector region and a buffer layer on the back surface of the semiconductor substrate of the first conductivity type,

[0044] The first step is to carry out the manufacturing process of the collector region of the second conductivity type, including the implantation process and the formation process. The implantation process is: the first type of ion implantation is performed from the back of the semiconductor substrate of the first conductivity type; the formation process is: performing laser annealing on the semiconductor substrate, thereby forming a first region of the second conductivity type having a higher carrier concentration than the semiconductor substrate of the first conductivity type on the back surface of the semiconductor substrate;

[0045] The second step is to perform a buffer layer manufacturing process, including an implantation process a...

Embodiment 3

[0051] Figure 1 to Figure 6 A first embodiment of the present invention is shown. Such as figure 1 As shown, the semiconductor device IGBT has completed all the front-side processes of the chip, including the trench gate MOS structure, and the back-side thinning process. After thinning, the chip thickness is 120 μm. The first conductivity type is n-type, the second conductivity type is p-type, the semiconductor silicon substrate is the n-type drift region 101 of the device, and the carrier concentration of the drift region 101 is 7E13cm -3 The formed front structure includes an n-type emitter region 102, a p-type base region 103, a trench gate 104, a gate oxide 105, an insulating layer 106 and a front metal electrode 107, and the front power MOS structure is manufactured using the front structure of a semiconductor device. General methods and conventional means are not described in detail here. The backside process starts with thinning the backside of the semiconductor sub...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention relates to the field of semiconductor device manufacture and in particular to a back side processing method of a power semiconductor device. The method comprises a first step ofperforming a second conductive type of collector region manufacturing process: implanting a first type of ions into the back side of the first conductive type of semiconductor substrate; performing alaser annealing treatment on the semiconductor substrate to form a second conductive type of first region having a higher carrier concentration than the first conductive type of semiconductor substrate on the back side of the semiconductor substrate; and a step of performing a buffer layer manufacturing process: performing proton implantation on the back side of the first conductive type of semiconductor substrate; and performing a annealing treatment on the semiconductor substrate. On the basis of performing proton implantation to form a buffer layer, the method performs an activation treatment after the ion implantation in the collector region in combination with a laser annealing method. Compared with the thermal annealing activation by implanting ions such as boron ions into the collector region, the laser annealing has a greatly increased activation rate, so that a higher collector region carrier concentration can be obtained while forming the buffer layer by proton implantation.

Description

technical field [0001] The invention relates to the manufacturing field of semiconductor devices, in particular to a back processing technology of power semiconductor devices. Background technique [0002] In semiconductor devices such as diodes or IGBT (insulated gate bipolar transistor), the n-type buffer layer is formed on the semiconductor substrate by proton implantation and relatively low-temperature thermal annealing. Due to the simple process, it has begun to be applied to the backside manufacturing process of the device. The conventional process of forming the collector area and buffer layer on the back of the semiconductor substrate is to perform proton implantation first, and then perform ion implantation of conventional acceptor elements (such as boron ions), or perform ion implantation of conventional acceptor elements (such as boron ions) first, Proton implantation is then performed, and then thermal annealing treatment is performed together, or thermal anneali...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/331H01L29/739H01L21/265
Inventor 王思亮胡强蒋兴莉
Owner 成都森未科技有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products