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A method for improving silicon wafer warpage and improving overlay accuracy

A technology of overlay accuracy and warpage, applied in the field of integrated circuit manufacturing, can solve problems such as the influence of wafer overlay accuracy

Active Publication Date: 2021-03-12
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Laser annealing has also been introduced into the manufacturing process of integrated circuits for ultra-shallow, high activation and low resistance, but it will have a negative impact on the stress of the wafer and the overlay accuracy of lithography

Method used

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  • A method for improving silicon wafer warpage and improving overlay accuracy
  • A method for improving silicon wafer warpage and improving overlay accuracy
  • A method for improving silicon wafer warpage and improving overlay accuracy

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Embodiment Construction

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0056] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0057] As a preferred embodiment, such as Figure 1-3 As shown, a method for improving the warpage of silicon wafers and improving the overlay accuracy, the film quality stress model used to obtain the stress data of silicon wafers, the relationship between the load effect of silicon wafers and t...

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Abstract

The invention discloses a method for improving the warpage of silicon wafers and improving the engraving accuracy. By adding specific auxiliary design graphics, the layout and pattern density are changed, so as to provide reverse stress or positive stress on the wafer. Then, in the subsequent chemical mechanical polishing process or etching process, by retaining the auxiliary design graphics, in order to achieve the purpose of changing the warpage of the wafer; at the same time, in order to ensure the release of the internal stress of the overall wafer Shot, through the photolithography process step The laser annealing process was introduced before, and the laser annealing energy and the size of the Shot were adjusted in a specific position in conjunction with the size of the photolithography shot to release the wafer stress and improve the overlay accuracy.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, relates to a layout data processing method, in particular to a method for improving the warping degree of a silicon chip and improving the engraving precision. Background technique [0002] With the continuous reduction of lithographic feature size, the requirements for overlay accuracy and critical dimension uniformity of lithography machines are also increasing. The manufacture of integrated circuits usually includes dozens of photolithography processes. In order to ensure the corresponding relationship of each level, it is necessary to require an overlay accuracy that matches the photolithography feature size. The difference between the exposure pattern and the actual position, that is, the pattern position offset, is an important factor affecting the overlay accuracy of the lithography machine, and is also an important factor affecting the device. [0003] The overlay accuracy...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F7/20
Inventor 孟鸿林姜立维陈翰张辰明
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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