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Semiconductor structure forming method

A semiconductor and gate structure technology, applied in the field of semiconductor structure formation, can solve the problem that the electrical performance of the semiconductor structure needs to be improved, etc., to improve the dielectric relaxation problem, the positive bias voltage-temperature instability characteristic and the negative bias voltage- The effect of improving temperature instability characteristics and reducing the content of oxygen vacancies

Active Publication Date: 2017-05-03
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Although the introduction of high-k metal gates can improve the electrical properties of semiconductor structures to a certain extent, the electrical properties of semiconductor structures formed by existing technologies still need to be improved.

Method used

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  • Semiconductor structure forming method
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  • Semiconductor structure forming method

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Embodiment Construction

[0032] As mentioned in the background art, the electrical performance of the semiconductor structure formed in the prior art needs to be improved.

[0033] It has been found through research that although the use of a high-k gate dielectric material as the material of the gate dielectric layer can improve the electrical performance of the semiconductor structure to a certain extent, for example, the leakage current (leakagecurrent) in the semiconductor structure is reduced, however, the semiconductor structure The relaxation current (DR Current, DielectricRelaxation Current) is still large, resulting in poor electrical performance of the semiconductor structure, for example, the positive bias-temperature instability characteristics (PBTI, Positive Biase Temperature Instability) and negative bias-temperature instability of the semiconductor structure The stability characteristic (NBTI, Negative Biase Temperature Instability) is remarkable. Further studies have found that the re...

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Abstract

The invention discloses a semiconductor structure forming method. The method comprises steps: a substrate is provided; an interface layer is formed on the surface of the substrate; first annealing treatment is carried out on the interface layer, and the first annealing treatment is carried out in a nitrogen-containing atmosphere to enable a nitrogen-containing layer to be formed on the surface of the interface layer; a high k gate dielectric layer is formed on the surface of the nitrogen-containing layer; second annealing treatment is carried out on the high k gate dielectric layer to enable nitrogen ions to be diffused to the high k gate dielectric layer; and a gate electrode layer is formed on the surface of the high k gate dielectric layer. The dielectric relaxation problem of the high k gate dielectric layer is improved, and thus, the electrical performance of the formed semiconductor structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] The main semiconductor device of an integrated circuit, especially a very large scale integrated circuit, is a metal-oxide-semiconductor field effect transistor (MOS transistor). With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are continuously reduced, and the geometric dimensions of semiconductor structures are continuously reduced following Moore's law. When the size of the semiconductor structure is reduced to a certain extent, various secondary effects caused by the physical limit of the semiconductor structure appear one after another, and it becomes more and more difficult to scale down the feature size of the semiconductor structure. Among them, in the field of semiconductor manufacturing, the most ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/06H01L29/40H01L21/336
CPCH01L29/0603H01L29/4236H01L29/42364H01L29/66477H01L29/78H01L29/66795H01L29/518H01L21/0214H01L21/02148H01L21/02164H01L21/0217H01L21/02178H01L21/02181H01L21/02189H01L21/02194H01L21/02247H01L21/02255H01L21/02332H01L21/02359H01L21/28158H01L29/513H01L29/517H01L29/66545
Inventor 李勇洪中山
Owner SEMICON MFG INT (SHANGHAI) CORP
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