Chip Separation Method for 3D Stacked Chip Packaging Devices

Abstract

The invention discloses a chip separation method for a 3D stacked chip encapsulator. The method comprises the steps that acoustic scanning micro-detection is conducted on the internal structure of a 3D stacked chip encapsulated ULSI sample to determine a region to be ground and the area of the region to be ground; the 3D stacked chip encapsulated ULSI sample is fixed to a grinding table through hot molten wax; grinding is conducted, wherein a grinding drill bit, the grinding intensity and the grinding direction are selected according to the area of the ground region, an encapsulating material and chips are removed, and the region is ground to a protective layer covering the surface of a target chip; a chemical etching method is adopted to remove the protective layer. According to the chip separation method, grinding is used as a main mode, and chemical etching is used as an auxiliary mode; a specific local region is removed through grinding, and the internal structure of the lower chips and bonding wires of the lower chips are not damaged; the protective layer covering the surface of the target chip or chip binder is removed through the chemical etching method, and then the target chip is exposed; the internal structure of the obtained target chip and the bonding wire on the target chip are complete and not damaged, and therefore subsequent electrical logging analysis is facilitated.

Description

technical field [0001] The invention relates to a chip separation method, in particular to a chip separation method for a 3D stacked chip packaging device. Background technique [0002] 3D stacked chip packaging technology uses a three-dimensional space to realize multi-chip interconnection. Under the premise of not changing the size of the package, it can be stacked in the same package in the vertical direction by wire bonding or TSV interconnection. Two or more chips. 3D stacked chip packaging ultra-large-scale integration (ULSI) has greatly reduced the power consumption of the circuit while improving the circuit performance, and has become a new favorite of high-performance devices. [0003] At present, for brand new 3D ULSI products, its internal structure is sometimes checked through destructive physical analysis, which requires exposing the multi-layer chips inside the 3D ULSI layer by layer, and internal visual inspection of the internal structure of each layer, so t...

AI Technical Summary

Problems solved by technology

The mechanical unsealing method is mainly used for the unsealing of ceramic cover plate packaging or metal shell packaging devices. The material of the packaging shell is removed by grinding or prying to expose the inner cavity of the package, but this method cannot unseat the chip in the package cavity. Partial processing and leaving the leads intact

[0006] Therefore, traditional chemical etching or mechanical unsealing methods cannot meet the needs of physical analysis of ULSI non-top chip in 3D stacked chip packaging

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