Soft Error Tolerant Scan Chain Flip-Flops

A flip-flop and soft error technology, applied in the direction of dynamic coding, etc., can solve problems such as complex control timing and unfavorable ATE testing, and achieve the effects of optimizing control timing, reducing area, and reducing delay

Inactive Publication Date: 2017-10-03
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0017] pass image 3 and Figure 4 It can be seen that the control timing of this soft-error-tolerant scan chain flip-flop is very complicated when scanning the test mode: four control clocks SCA, SCB, UPDATE and CAPTURE are required, and the rising edge sequence of these clocks needs to be carefully design
This is very bad for ATE testing

Method used

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  • Soft Error Tolerant Scan Chain Flip-Flops
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Embodiment Construction

[0040] The soft-error tolerant scan chain flip-flop proposed by the present invention will be described in detail below with reference to the drawings and embodiments.

[0041] The present invention provides a scan chain flip-flop that can tolerate soft errors, including a multiplexer (MUX), a parallel flip-flop module (Multi-FF), a soft error processing unit (C-element) and a holding circuit (Keeper) . Its structure diagram is as follows Figure 5 shown.

[0042] The soft-error-tolerant scan chain flip-flop provided by the present invention has three working modes, which are fault-tolerant mode, scan test mode and low power consumption mode.

[0043] Due to the existence of the C-element, the soft-error tolerant scan chain flip-flop provided by the present invention needs to be connected to an inverter at the output end when it is actually used. The circuit provided by the present invention is simulated and analyzed by using HSPICE, the simulation experiment is based on TS...

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Abstract

The invention relates to the field of reliability of integrated circuit technology. A soft-error tolerant scan chain flip-flop is disclosed, including a multiplexer (MUX), a parallel flip-flop module (Multi‑FF), a soft error processing unit (C‑element) and a holding circuit (Keeper). The soft-error-tolerant scan chain flip-flop provided by the present invention has three working modes, which are fault-tolerant mode, scan test mode and low power consumption mode. Compared with the existing scan chain flip-flop (EC design) that can tolerate soft errors, the present invention has the same function under the premise of improved performance (area, power consumption, delay), and simplifies the control during scan test The timing is simplified from 4 control clocks to 1 control clock, making it easier to apply to normal ATE scan tests.

Description

technical field [0001] The invention relates to the reliability field of integrated circuits, in particular to a scan chain flip-flop that can tolerate soft errors. Background technique [0002] From the perspective of the development of integrated circuits, high reliability is the commanding height of integrated circuit design from beginning to end. Integrated circuits have been widely used in safety-critical fields such as banking, communication, medical treatment, industrial control, aerospace and military. Therefore, the high reliability design of integrated circuits has become a new focus of attention. Since 80% to 90% of chip failures are caused by soft errors, soft error tolerance technology has become a very critical link in the high reliability design of integrated circuits. [0003] Soft errors can be defined as erroneous changes that do not change the physical circuit but only change the data content. The main cause of soft errors is radiation, such as ray ion r...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M11/20
Inventor 王秋实冯建华
Owner PEKING UNIV
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