A vertical double diffusion field effect transistor and its manufacturing process

Abstract

In one embodiment, a method of making a VDMOS transistor can include: (i) etching an oxide layer formed on a surface of an epitaxial structure to define an active region of the VDMOS; (ii) injecting and diffusing a first dopant into the active region to form a doping region; (iii) forming a gate oxide layer on the active region; (iv) depositing polysilicon on the gate oxide layer, and etching the polysilicon to form a gate; (v) injecting a second dopant at an end of the gate to form a source, where the first and second dopants have opposite types; (vi) forming a contact hole adjacent to the gate, and injecting a third dopant into the contact hole, where the first and third dopants have a same type; (vii) depositing and etching aluminum on a chip surface; and (viii) coating the aluminum and chip surface with a passivation layer.

Description

technical field [0001] The invention belongs to the field of semiconductor devices, in particular to a vertical double-diffusion field effect transistor and a manufacturing process thereof. Background technique [0002] Vertical double-diffusion MOS (VDMOS) has the advantages of both bipolar transistors and ordinary MOS devices. It has nearly infinite static input impedance characteristics and very fast switching time. Therefore, whether it is a switching application or a linear application, They are all ideal power devices, which can be mainly used in motor speed regulation, inverter, uninterruptible power supply, electronic switch, hi-fi audio, automotive electrical appliances and electronic ballast. However, in the existing vertical double-diffused field-effect transistor manufacturing process, the step of padding polysilicon (Poly) to form the gate is generally set before the formation of the doped body region, so that although only one photolithography is required, the ...

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Problems solved by technology

[0003] The purpose of the present invention is to provide a vertical double diffused field effect transistor and its manufacturing process to solve the breakdown voltage drop and leakage problems caused by the self-aligned implantation of the depleted channel in the prior art

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