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Preparation method of gate oxide integrity (GOI) wafer structure

A wafer and layered structure technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of high dislocation density and complex process of GOI wafers, and achieve improved germanium concentration technology, simple process, and reduced penetration dislocation effect

Active Publication Date: 2014-04-23
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a method for preparing a GOI wafer structure, which is used to solve the problems of complex processes and high dislocation density in the GOI wafer in the prior art

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  • Preparation method of gate oxide integrity (GOI) wafer structure
  • Preparation method of gate oxide integrity (GOI) wafer structure
  • Preparation method of gate oxide integrity (GOI) wafer structure

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Embodiment Construction

[0042] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] see Figure 1a to Figure 1f ,as well as Figure 2 to Figure 3 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion...

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Abstract

Provided is a method for fabricating a GOI wafer structure, the method comprising: firstly utilizing Smart-Cut technology to fabricate an SGOI wafer structure, and then conducting germanium concentration on the SGOI wafer structure to obtain the GOI wafer structure. The SGOI fabricated by the Smart-Cut technology basically has no mismatching or dislocation on an SGOI / BOX interface, thus ultimately reducing the penetrating dislocation of the GOI. The present invention has a simple process, and can fabricate high quality GOI wafer structure, thus greatly improving germanium concentration technology. With ion injection technology and annealing technology both being highly mature processes in the current semi-conductor industry, the fabrication method greatly improves the possibility of widely applying germanium concentration in the semi-conductor industry.

Description

technical field [0001] The invention relates to a method for preparing a wafer structure, in particular to a method for preparing a GOI wafer structure. Background technique [0002] With the rapid development of silicon-based large-scale integrated circuit technology, the performance of bulk silicon CMOS devices has gradually approached the physical limit of silicon materials, and further improving the performance of bulk silicon CMOS devices in the direction guided by Moore's law will face increasing investment and market risk. The semiconductor industry is a market that is very sensitive to the performance-price ratio of products. How to continuously improve the performance of silicon-based devices based on the existing VLSL process without increasing investment has become a common problem in the industry. The exploration of new materials and new processes is undoubtedly an important way of thinking and research direction to solve this problem. [0003] Germanium-on-in...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
CPCH01L21/76254
Inventor 张苗叶林狄增峰薛忠营
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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