Preparation method of horizontal phase change storage irrelevant to photoetching resolution ratio

Abstract

A preparation method of a horizontal phase change storage irrelevant to photoetching resolution ratio comprises sequentially growing an electric heating insulation material layer, a phase change material layer and a sacrifice material layer on a substrate; forming steps for preparing lateral walls through photoetching and dry etching methods; depositing on the upper surface of a shape-protection covering sample of a lateral wall material; etching a lateral wall material layer in returning mode in a dry method, removing the lateral wall material layer, forming a lateral wall with the height and the width in nanoscale; using wet etching to remove the sacrifice material layer, etching the phase change material layer in a dry method and forming a nanowire of the phase change material; preparing an anticorrosive electrode material layer at one edge of the lateral wall material layer and transversely striding a longitudinal lamination nanowire structure constructed by the sacrifice material layer and the lateral wall material layer; conducting wet etching to remove the lateral wall material layer; conducting dry etching to remove the phase change material layer outside the position below the electrode material layer through a metal electrode material layer mask; and peeling to form a structure that the phase change material layer is all limited between the electrode material layer, passivating and leading out a test electrode, and completing preparation of devices.

Description

technical field [0001] The invention relates to the field of micro-nano technology, in particular to a preparation method of a horizontal phase change memory independent of lithography resolution. The present invention provides a method for self-aligning and preparing a horizontal fully confinement phase change memory device by adopting a sidewall process and an ultrasonic-stripping process. This method avoids the disadvantages of high cost and long period of linear lithography methods such as electron beam exposure and focused particle beam etching as much as possible, breaks through the limitation of optical lithography resolution, and is suitable for nanoscale devices on large-area substrates. The preparation has great advantages in preparation accuracy, preparation efficiency, economy and compatibility with existing CMOS processes. Background technique [0002] The accelerated development of high-tech industries and infrastructure service facilities requires higher and ...

AI Technical Summary

Problems solved by technology

At present, the main problem faced by phase change memory is that the operating current is too large and the requirements for the drive circuit are high, which limits the reduction of storage power consumption, the improvement of storage speed and the increase of storage density.

For the technical bottleneck of excessive PCRAM operating current, conventional solutions (such as the preparation of plug electrodes in vertical devices) are highly dependent on optical lithography resolution, CMP, MOCVD and other processes, and it is difficult to achieve large-area, high-precision , economical and efficient preparation

Although linear processing technologies such as electron beam exposure and focused particle beam etching with high preparation precision can achieve high preparation precision, they cannot achieve efficient preparation of fine patterns on large-area substrates due to the limitation of processing speed.

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