Reducing the creation of charge traps at gate dielectrics in mos transistors by performing a hydrogen treatment

Abstract

By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]Generally, the present disclosure relates to sophisticated integrated circuits, such as CPUs including scaled transistor elements, and, more particularly, to performance-reducing charge trap creation at the interface between the gate dielectric material and the channel region.[0003]2. Description of the Related Art[0004]The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, MOS technology is currently one of the mo...

AI Technical Summary

Benefits of technology

[0012]Generally, the subject matter disclosed herein relates to techniques and semiconductor devices in which the stress-related shift of threshold voltage over time in advanced field effect transistors, in particular in P-channel transistors, may be reduced by conditioning an exposed silicon-containing surface of a semiconductor layer prior to the formation of gate dielectric materials, such as silicon dioxide based gate insulation layers or any other sophisticated gate dielectric materials, in order to enhance the characteristics of the crystalline material in the vicinity of the surface, thereby also enhancing the interface formed with the gate dielectric material. Furthermore, due to the enhanced surface and near-surface crystallinity of the semiconductor material, the quality of the gate dielectric material may be enhanced, which may also contribute to a reduced number of charge traps that may affect the threshold voltage, as previously explained. Without intending to restrict the present application to the following explanation, it is believed that, due to the superior quality of the crystalline semiconductor material in the vicinity of the interface between the gate dielectric material and the silicon-containing semiconductor material and the enhanced quality of the gate dielectric material itself, the creation of respective charge traps during the occurrence of any stress conditions, such as the static and dynamic application of negative bias, high temperature and the like, may be reduced, thereby also improving threshold voltage degradation over the lifetime of the device. Hence, increased flexibility may be obtained for designing the overall circuit layout, since less pronounced margins with respect to threshold degradation may have to be taken into consideration.

Problems solved by technology

Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors.

The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length.

Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region.

Although generally high speed transistor elements having an extremely short channel may preferably be used for high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may represent limitations for performance-driven circuits.

This effect, also referred to as “negative bias temperature instability (NBTI),” is mainly present in PMOS transistors and was not considered particularly relevant for semiconductor devices in the following years due to the low influence on the overall device performance of devices, in particular as NMOS devices have increasingly been developed.

This situation changed with the introduction of complex CMOS devices including high performance logic circuits, in which millions of signal nodes with PMOS and NMOS transistors are typically provided.

Moreover, the operating states resulting in the application of a negative voltage to the gate electrode of a PMOS transistor may depend on the signal path considered and the overall operational conditions, thereby making the threshold shift highly non-predictable and hence requiring appropriately set design criteria to ensure the desired performance of the transistors over the entire specified lifetime of the device.

For example, a shift of the threshold voltage over the accumulated operating time may finally lead to violation of the timing specification of the device, which may not allow further use of the device despite the fact that no other major failure has occurred.

That is, upon negative gate voltage, elevated temperature and other stress conditions, a charge trap may be created in the vicinity of the interface by an interface state, thereby causing holes to be trapped.

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