Context switch data prefetching in multithreaded computer

Abstract

An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a divisional of U.S. patent application Ser. No. 10 / 739,738 filed on Dec. 18, 2003 by Jeffrey P. Bradford et al. In addition, this application is related to U.S. patent application Ser. No. 10 / 739,739, filed Dec. 18, 2003, Jeffrey P. Bradford et al., and entitled “CONTEXT SWITCH INSTRUCTION PREFETCHING IN MULTITHREADED COMPUTER” (ROC920030286US1) and U.S. patent application Ser. No. ______, filed on even date herewith by Jeffrey P. Bradford, et al. (ROC920030285US2), which is also a divisional of the aforementioned '738 application. The entire disclosures of each of these applications are incorporated by reference herein.FIELD OF THE INVENTION[0002]The invention relates to computers and computer software, and in particular to prefetching of instructions and data in a multithreaded computer system.BACKGROUND OF THE INVENTION[0003]Given the continually increased reliance on computers in contemporary society, computer tec...

AI Technical Summary

Benefits of technology

[0018]The invention addresses these and other problems associated with the prior art by initiating, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. Put another way, once it is known that a context switch will be performed to a particular thread, embodiments consistent with the invention initiate prefetching of data on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory. As a result, in many instances the cache-related performance penalties associated with context switching can be reduced, and thus overall system performance can be increased.

Problems solved by technology

While multithreading in this nature can significantly increase system performance, however, some inefficiencies exist as a result of switching between executing different threads in a given execution path.

One undesirable side effect of performing a context switch in many environments, however, is the increased occurrence of cache misses once a thread is switched back in.

Often, a computer relies on a relatively large, slow and inexpensive mass storage system such as a hard disk drive or other external storage device, an intermediate main storage memory that uses dynamic random access memory devices (DRAM's) or other volatile memory storage devices, and one or more high speed, limited capacity cache memories, or caches, implemented with static random access memory devices (SRAM's) or the like.

Whenever a memory access request attempts to access a memory address that is not cached in a cache memory, a “cache miss” occurs.

As a result of a cache miss, the cache line for a memory address typically must be retrieved from a relatively slow, lower level memory, often with a significant performance hit.

However, given that the same premise applies to all of the threads executing in a multithreaded computer, whenever a thread is suspended as a result of a context switch, and then is later resumed as a result of another context switch, it is likely that some or all of the instructions and data that were cached prior to suspending the thread will no longer be cached when the thread is resumed (principally due to the caching of instructions and data needed by other threads that were executed in the interim).

A greater number of cache misses then typically occur, thus negatively impacting overall system performance.

Prefetching and branch prediction, which rely on historical data, also typically provide little or no benefit for a resumed thread upon its initial resumption of execution, as the prefetching of instructions and data cannot be initiated until after the thread resumes its execution.

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