Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers

Abstract

Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.

Description

FIELD OF THE INVENTION [0001] The present invention relates to complementary metal oxide semiconductor (CMOS) integrated circuits, and more particularly to three-dimensional CMOS integrated circuits having semiconductor device layers that are built on different crystal oriented wafers. BACKGROUND OF THE INVENTION [0002] In present semiconductor technology, CMOS devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation. [0003] Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron hole mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger...

AI Technical Summary

Benefits of technology

[0011] The present invention provides a three-dimensional (3D) integration scheme of fabricating a 3D integrated circuit in which the pFETs are located on a (110) crystallographic surface and the nFETs are located on a (100) crystallographic surface. The term “3D integrated circuit” can be defined as an IC that contains multiple layers of active devices with vertical interconnections between the layers. In a 3D IC, each transistor can access a greater number of nearest neighbors than in a conventional two-dimensional (2D) circuit, such that each transistor or functional block will have a higher bandwidth.

[0012] One advantage of 3D integration is increased packing density; by adding a third dimension to the conventional 2D layout, the transistor packing density can be improved thereby allowing a reduced chip footprint. This is particularly appealing for wireless or portable electronics. Another advantage of 3D integration is that the total interconnect lengths are shorten. This provides shorter interconnect delays, less noise and improved electro-migration reliability. A further benefit of 3D integration is that the overall chip performance at a given power consumption can be substantially improved over a conventional 2D IC.

Problems solved by technology

To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching pFETs having larger widths are undesirable since they take up a significant amount of chip area.

Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.

As can be deduced from the above discussion, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices.

It is becoming more difficult to achieve substantial integrated circuit (IC) performance enhancement by traditional CMOS device and interconnect scaling.

New materials introduced into the front-end and back-end of IC fabrication are enabling the continuation of the performance trends, but such innovations may provide only a one-time or a short-lived boost, and fundamental physical limits may soon be reached.

Circuits fabricated in this manner suffer from two main drawbacks: (1) the recrystallized top layer often has poor electrical properties and it may result in lower device and circuit performance; it is also difficult to control the surface orientation of the recrystallized layer; (2) the thermal cycling from the top layer formation and sequential device fabrication degrades underlying device performance.

Despite these current advances using 3D integration, there is no prior art that fabricates 3D integrated circuits having nFETs and pFETs which are built on different surface orientations.

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