Streamlined convolution computing architecture design method and residual network acceleration system

Abstract

The invention provides a streamlined convolution computing architecture design method and a residual network acceleration system. According to the method, a hardware acceleration architecture is divided into an on-chip buffer area, a convolution processing array and a point-by-point addition module; a main path of the hardware acceleration architecture is composed of three convolution processing arrays which are arranged in series, and two assembly line buffer areas are inserted among the three convolution processing arrays and used for achieving interlayer assembly lines of three layers of convolution of the main path. A fourth convolution processing array is set to be used for processing convolution layers, with the kernel size being 1 * 1, of the branches of the residual building blocks in parallel, a register in the fourth convolution processing array is configured, the working mode of the fourth convolution processing array is changed, the fourth convolution processing array can be used for calculating a residual network head convolution layer or a full connection layer, and when the branches of the residual building blocks are not convolved, the fourth convolution processing array is skipped out and convolution is not exected; and a point-by-point addition module is set to add corresponding output feature pixels element by element for the output feature of the main path of the residual building block and the output feature of the branch quick connection.

Description

technical field [0001] The present invention relates to the field of computer vision scene processing methods, and more specifically, to a method for designing a pipeline convolution computing architecture and a residual network acceleration system. Background technique [0002] Convolutional neural networks (CNNs) are widely used in various computer vision scenarios and have shown superior performance. However, due to complex and intensive computing requirements and huge storage requirements, it is a challenge to deploy and accelerate convolutional neural networks on mobile devices and embedded platforms that are sensitive to power consumption and require high real-time performance. [0003] In the convolutional neural network, the calculation time of the convolutional layer occupies more than 90% of the total calculation time of the network. Therefore, the acceleration of the convolutional layer operation is the most important part of the acceleration of the convolutional ...

AI Technical Summary

Problems solved by technology

However, due to the need to access an external memory before and after the calculation of each layer of convolution calculation, and the residual network usually has a deep network layer, it brings a lot of energy consumption and memory access delay; due to the residual Due to the particularity of the network structure, using a single convolution processing array can only serially execute the convolution layer connected by the main road of the residual building block and the branch shortcut, and then perform point-by-point addition, which cannot make full use of the parallelism of its structure; At the same time, the residual network convolution layer has various sizes, and using a single convolution processing array to process convolutions of different sizes usually cannot achieve high hardware resource utilization.

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