Clock switching circuit of gigabit Ethernet transceiver

Abstract

The invention provides a clock switching circuit of a gigabit Ethernet transceiver. According to the circuit, smooth switching of different clock domains is achieved through a three-level synchronization and interlocking mechanism, the risk that burrs and metastable states are generated due to clock switching across the clock domains is avoided, the correctness of circuit functions is guaranteed,a correct output clock can be provided during resetting, and the logic function of a chip during resetting is guaranteed.

Description

technical field [0001] The invention belongs to the field of computer communication and network, and relates to a clock switching circuit of a Gigabit Ethernet transceiver, which is especially suitable for the fields of Ethernet controllers, network servers, computer data storage systems and the like. For example, data service centers, large switches, etc. It is suitable for circuit design with high integration and low overhead. Background technique [0002] Gigabit Ethernet supports two transceivers, gphy and serdes, and gphy supports three rates of 10 / 100 / 1000Mbps; when working, users can choose between gphy and serdes according to their needs, and the communication rate of gphy can be 10M, Switch between 100M and 1000M. However, selecting different transceivers and different communication rates involves dynamic switching of clocks across clock domains, and the three switching clocks and control signals come from different clock domains. How to achieve correct switching ...

AI Technical Summary

Problems solved by technology

However, choosing different transceivers and different communication rates involves dynamic switching of clocks across clock domains, and the three switching clocks and control signals come from different clock domains. How to achieve correct switching of clocks across clock domains while avoiding metastability or generating clock glitches is a critical issue that needs to be addressed

[0003] The prior art generally selects the MUX selection circuit, and this method is generally used in circuits that do not have strict requirements on the clock system; however, due to the difference in input clock frequency and phase, As well as the asynchronous switching signal and clock, it is easy to cause glitches in the output clock during the switching process

[0004] The patent document "A glitch-free switching circuit supporting N clocks (CN201610008589.9)" discloses a clock switching scheme, but the number N of clocks to be switched must be is the power of 2, when N is an odd number, this scheme cannot be used

[0005] Patent documents "A Clock Switching Circuit (ZL200710098961.0)", "A Clock Switching Circuit (ZL200810067535.5)", "Clock Switching Circuit (ZL200810068164. 2)" and "A Clock Switching Method and Clock Switching Device (ZL201010560049.4)" all disclose glitch-free clock switching schemes, but the above-mentioned various schemes only support the dynamic switching of two clocks

[0006] The patent document "A Clock Switching Device (ZL201410310730.1)" proposes a glitch-free switching scheme that supports multiple clocks, but this scheme only allows the clock frequency Sequential switching from high to low or low to high, skipping clock switching is not supported

[0007] None of the prior art described above can generate the correct output clock according to the functional requirements of the Gigabit Ethernet circuit during reset

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