Damascus interconnection process

Abstract

The invention relates to a Damascus interconnection process, and relates to semiconductor integrated circuit manufacturing process. Back etching process is carried out on a metal hard mask layer pattern, a second cap layer is deposited, the second cap layer covers the side wall of the metal hard mask layer, and the second cap layer covering the side wall of the metal hard mask layer is always reserved to the cleaning process, so that the chance that the side wall of the metal hard mask layer is in contact with the atmospheric environment and reacts with water vapor in the air to generate a compound is avoided, the copper filling defect is reduced, and the yield of the semiconductor device is further improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process, in particular to a damascene interconnection manufacturing process. Background technique [0002] In semiconductor manufacturing technology, as the size of devices continues to shrink, the industry generally uses Damascus interconnection technology. In Damascus copper interconnection technology, it is necessary to etch the device to form copper interconnection trenches, and then deposit a copper diffusion barrier layer to cover the copper. The inner surfaces of the interconnection trenches are then filled with metal copper and subjected to chemical mechanical polishing to obtain the desired structure. [0003] In addition, as the critical dimension (CD) of the back-end process decreases, a metal hard mask (metal hard mask, MHM, such as TIN) is gradually used in the damascene interconnection process. Some semiconductor foundries start using metal hard masks from 65nm. I...

AI Technical Summary

Problems solved by technology

However, in the damascene interconnection process, the metal hard mask layer is easy to react with the water vapor in the air to form compounds, which will lead to subsequent copper filling defects, which will lead to a decrease in the yield of semiconductor devices

[0004] Specifically, see Figure 1a-1b , Figure 1a-1b A schematic diagram of the generation of defects in the metal hard mask layer in the prior art, such as Figure 1a peeling of the metal hard mask layer shown results in the Figure 1b Copper defects shown

Images