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Use of Dimashg process in production of integrated circuits

An integrated circuit and process technology, which is applied in the field of integrated circuit manufacturing with Damascus technology, can solve the problems of complex etching process, adverse reactions in the subsequent process, cumbersome process, etc., to reduce the occurrence of filling defects, reduce capacitance, and simplify the process required effect

Inactive Publication Date: 2010-05-12
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

Full VIA First (Full VIA First) This process has no alignment problems, no via failure problems and a large process window, but the problem is mainly concentrated in the via filling step, failed via filling or uneven filling The performance will inevitably lead to adverse reactions in the subsequent process, or even failure, and the conventional filling reagent and subsequent photolithography process use a variety of different types of chemical substances, the process is cumbersome, and the subsequent etching process is complicated

Method used

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  • Use of Dimashg process in production of integrated circuits
  • Use of Dimashg process in production of integrated circuits
  • Use of Dimashg process in production of integrated circuits

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Embodiment Construction

[0036] Now in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail:

[0037] Firstly, a through-hole dielectric layer 1 at the bottom layer of damascene is deposited.

[0038] Secondly, if Figure 3A as shown ( Figure 3A For the schematic diagram of coating the first single-layer photosensitive material), the first layer of single-layer photosensitive material 3 is coated on the surface of the through-hole dielectric layer of the damascene bottom layer, and photolithography is performed. The first single-layer photosensitive material is composed of ketones, ethers, alkane organic solvents and photosensitive cross-linking resins, and the molecular weight is between 85,000 and 150,000.

[0039] Secondly, if Figure 3B as shown ( Figure 3B is a schematic diagram of through-hole etching), and through-hole etching and cleaning are performed on the bottom layer of the Damascus through-hole dielectric layer. The et...

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Abstract

The method comprises: a intercombination of a double layer light sensitiveness material and a signal layer light sensitiveness material is used to make Damascus through hole; a bottom layer antireflection fulfilling materials of double layer light sensitiveness material is used to fill up the through hole, and making etch-back; making multi times coating and multiple baking for the top light sensitiveness low dielectric constant material of the double layer light sensitiveness material; based on light etching, developing and plasma surface hardening treatment, namely a Damascus Process adopting non chemical reaction etching means, a fabrication using Damascus Process is achieved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit technology, and in particular relates to a method for manufacturing integrated circuits by combining double-layer photosensitive materials and single-layer photosensitive materials and using Damascus technology for step-by-step manufacturing of through holes and metal wires. Background technique [0002] With the continuous improvement of integrated circuit manufacturing technology, the volume of semiconductor devices is becoming smaller and smaller, which makes the parasitic capacitance between metals more and more large. For microprocessors, the chip speed is mainly limited by the resistance and Parasitic capacitance is produced. As a result, problems such as resistance-capacitance time delay, mutual interference between signals, and energy loss have become increasingly prominent. In order to solve the problem of resistance-capacitance time delay, the industry's response has always be...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/3205
Inventor 朱骏
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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