A mram memory chip using fully depleted silicon-insulator fd-soi field effect transistor

Abstract

The invention discloses an MRAM memory chip using a fully depleted silicon-insulator FD‑SOI field effect transistor and a design method for adjusting gate potential. The field effect transistor of each MRAM memory unit in the MRAM memory array Silicon-as-insulator FD‑SOI field effect transistor, including a bulk potential control unit. The value V of the back gate potential V_body of the FD‑SOI field effect transistor in the working state b It can be flexibly configured as any value within an appropriate range. When writing the direction of 0 in the design method: the source line potential V_SL is set to V 0 +V b , the bit line potential V_BL is set to 0, and the gate (word line) potential V_G is set to V dd +V b . When writing 1 direction: the source line potential V_SL is set to V b , the bit line potential V_BL is set to V 1 +V b , the gate (word line) potential V_G is set to V dd +V b . The invention can eliminate the latch effect existing in the bulk silicon field effect transistor, can adjust the potential of the back gate, and solves the problem of insufficient driving current provided by the writing circuit.

Description

technical field [0001] The invention belongs to the technical field of semiconductor chip storage, in particular to an MRAM memory chip using fully depleted silicon-insulator FD-SOI field effect transistors. Background technique [0002] Magnetic Random Access Memory (MRAM) is an emerging non-volatile storage technology. It has high-speed read and write speed and high integration, and can be rewritten infinitely. MRAM can be read and written as fast as SRAM / DRAM, and can permanently retain data after power failure like Flash memory. [0003] MRAM has good economy and performance, and its unit capacity of silicon chip area has a great advantage over SRAM, and also has advantages over NOR Flash, which is often used in such chips, and has greater advantages than embedded NOR Flash. . The MRAM read and write delay is close to the best SRAM, and the power consumption is the best among various memory and storage technologies; and MRAM is compatible with standard CMOS semiconduc...

AI Technical Summary

Problems solved by technology

This is because once the body potential of the back gate is raised in the bulk silicon field effect transistor, a current will be generated in the back gate of the back gate, and the two sets of source, drain and back gate of the adjacent two NMOS and PMOS transistors A set of NPN and PNP triode loops will be formed in the pole, and the back gate current will be amplified by positive feedback, so that the field effect tube will not work properly or even have the risk of burning

In addition, if the source or drain is at 0 potential when the back gate potential is raised, the forward conduction of the PN junction will occur between the source or drain and the back gate, making the field effect transistor unable to work normally.

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