Implementation method of multi-valued memory

Abstract

The present invention proposes a method for implementing a multi-valued memory, which includes: a multi-valued storage area composed of multiple storage modules; a row decoding module; a column writing circuit module with D / A conversion and a circuit module with A / D conversion A column readout circuit module; wherein the memory module includes a plurality of memory cells and a reset drive circuit; the memory cell at least includes: a switch tube and a PN junction capacitor connected to the switch tube with surface potential pinning; The reset drive circuit at least includes: a reset transistor and a drive transistor.

Description

technical field [0001] The invention relates to the field of storage processing, in particular to a method for realizing a multi-value (multi-bit) memory. Background technique [0002] Data stored in a random access memory (RAM, random access memory) can be read or written on demand, and the speed of reading and writing has nothing to do with the storage location of the data. This kind of memory has the fastest read and write speed in the memory, but the stored data will be lost when the power is turned off, so it is mainly used to store short-term data. According to the different stored information, random access memory can be divided into static random access memory (Static RAM, SRAM) and dynamic random access memory (Dynamic RAM, DRAM). [0003] An existing SRAM such as figure 1 As shown, its storage unit is a flip-flop, which is composed of 6 MOS transistors, that is, the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, the fourth MOS...

AI Technical Summary

Problems solved by technology

The capacitor C1 of DRAM is generally formed in a stacked or trenched manner. The advantage is that it occupies a small area and can achieve a large capacity. The disadvantage is that the process is much more complicated than the logic circuit, and the access speed is slower than that of SRAM.

Another disadvantage of DRAM is that the memory cells are based on the amount of charge stored on capacitor C1, which decreases with time and temperature and must therefore be refreshed periodically to maintain the correct information they originally remembered

Another disadvantage of DRAM is that due to the conductive interconnection between capacitor C1 and MOS transistor M1, there is a contact hole for conductive interconnection, which needs to be in contact with the silicon surface when interconnecting with the MOS transistor. In this way, there will be an interface state at the contact interface between the contact hole and the silicon, and the electrons in the interface state are relatively active (plasma etching is required when making the contact hole, which will cause damage to the chip surface, and the contact of the two interfaces will be damaged at the same time. There are interface states. Due to the existence of interface states, there are a large number of defect centers on the surface, which makes it easy for carriers to be captured and released on the surface, which greatly increases leakage), and leakage is a problem that is very difficult to control, (increased leakage will lead to refresh The time is shortened and the power consumption is increased), and DRAM and SRAM will have reset noise when reading and writing

[0005] From the above analysis of the existing technology, it can be seen that the performance of the existing SRAM and DRAM has defects

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