Power semiconductor device and preparation method thereof

Abstract

The invention provides a power semiconductor device and a preparation method thereof. The method comprises the steps of forming a gate oxidation layer, and depositing a polycrystalline silicon gate; performing first etching treatment; performing first ion injection treatment; performing second ion injection treatment; forming a thermal oxidation layer; performing third ion injection treatment; depositing an interlayer dielectric layer; performing second etching treatment; and sputtering front-surface metal. According to the preparation method of the power semiconductor device, provided by an embodiment of the invention, general photoetching selective injection is replaced with a thermal oxidation layer self-alignment process and contact etching, so that the process steps can be effectively reduced, the process control difficulty can be lowered, the P+ and N+ photoetching rework rates and the parameter fluctuation and deviation caused by the P+ photoetching alignment and N+ photoetching alignment problems are avoided, the device parameter stability is improved, and the product yield is increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a power semiconductor device and a preparation method thereof. Background technique [0002] Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), vertical double diffused metal-oxide semiconductor field effect transistor (VDMOS) is a commonly used power semiconductor device (also known as power electronic device), which has the ability to handle high voltage, High current capability has been widely used in frequency conversion, voltage conversion, current conversion, power management and so on. [0003] Existing IGBT, VDMOS (structural schematic diagram see figure 1 ) preparation process generally includes: P-implantation, P+ photolithography, P+ implantation, P+ glue removal, P- / P+ well annealing, gate oxide etching, N+ photolithography, N+ implantation, N+ glue removal, making interlayer dielectric layer , contact hole photolithography, etching,...

AI Technical Summary

Problems solved by technology

In such a preparation process, the alignment deviation problem of P+ lithography and N+ lithography will cause fluctuations and deviations of device parameters (such as Vth)

Especially when the design margin is low, the parameters fluctuate greatly, which will increase the difficulty of process control and cause a high lithography rework rate, and reduce the product yield

[0004] Therefore, the preparation process of current power semiconductor devices still needs to be improved.

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