Semiconductor substrate, three-dimensional package chip and through-silicon via packaging method

Abstract

The invention discloses a semiconductor substrate, a three-dimensional package chip and a through-silicon via packaging method. The semiconductor substrate has a through-silicon via running through the semiconductor substrate; the internal surface of the through-silicon via is circumferentially deposited by a conductive material, the thickness of which is smaller than 2 mum; the volume fraction of the conductive material in the through-silicon via is 5 vol.%-95 vol.%; and the center of the through-silicon via has a gap running through the through-silicon via. Only the internal surface of the through-silicon via is circumferentially deposited by the conductive material, and the center of the through-silicon via in the semiconductor substrate still has a certain gap, so that the prepared three-dimensional package chip does not deform easily under hot and cold environment, yield is improved, and the service life of the three-dimensional package chip is prolonged.

Description

technical field [0001] The invention belongs to the technical field of semiconductor manufacturing, and more specifically relates to a packaging method for a semiconductor substrate, a three-dimensional packaging chip and a through-silicon via. Background technique [0002] Through-Silicon-Via technology (Through-Silicon-Via, TSV) is the main method to realize the interconnection between chips by making vertical conduction between chips and wafers. important role in integrated circuits. [0003] The prior art TSV technology (Microelectronic Engineering, Volume 150, 25January 2016, Pages 39–42) such as figure 1 As shown: including drilling holes on the substrate, making insulating layers, barrier layers, and seed layers, and then using electroplating to generate conductive materials in the TSV holes, filling all the TSV holes, and then making a mask layer by photolithography. The surface circuit layer and pads are produced by sputtering, and finally the chip is packaged aft...

AI Technical Summary

Problems solved by technology

This method has the following disadvantages: 1. While filling the TSV with electroplating, conductive materials are also growing on the substrate surface around the TSV; after the filling is completed, a thick layer of conductive material will grow on the TSV hole and its surroundings, which needs to be carried out later. Long time CMP polishing removal, making the manufacturing process time-consuming and costly

2. Since the TSV hole is filled with conductive material, and the coefficient of thermal expansion (CTE) of the conductive material and the substrate is inconsistent, the substrate is prone to cracks at the TSV under thermal cycle and thermal shock conditions, resulting in chip failure

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