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Bipolar transistor epitaxial wafer manufacturing method adopting varied temperature and varied doping flow

A technology of bipolar transistors and manufacturing methods, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem of low growth rate growth temperature, influence of epitaxial layer doping concentration and vertical carrier distribution, and yield rate reduce the problem, achieve the effect of increasing the growth temperature and suppressing the graphics drift

Active Publication Date: 2016-02-24
NANJING GUOSHENG ELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, the double-buried layer epitaxy process has the following problems due to the existence of the buried layer: on the one hand, due to the existence of the buried layer pattern, in order to effectively suppress the pattern drift and distortion, it is necessary to maintain a low growth rate and a high growth temperature; On the other hand, due to the existence of P+ buried layer B, the evaporation effect of B is serious at high temperature, and the impurities in the buried layer will seriously affect the doping concentration of the epitaxial layer and the longitudinal carrier distribution, which will further lead to the deterioration of device performance and good performance. reduction in rate

Method used

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  • Bipolar transistor epitaxial wafer manufacturing method adopting varied temperature and varied doping flow

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Embodiment 1

[0026] Embodiment 1: The epitaxial equipment used in this embodiment is: PE2061S barrel type epitaxial furnace of Italian LPE Company. The specific steps of the method adopted in this embodiment are as follows: figure 1 As shown, the device material structure involved in this embodiment is as figure 2 Shown: the diameter is 6 inches, the P-type conductive substrate, the crystal orientation is , the resistivity is 8-13Ω·cm, the square resistance of the B buried layer area is 90Ω / □ (ohm per square), and the substrate is fabricated For N+ and P+ buried layers, the N-type impurity is Sb, the P-type impurity is B, the resistivity of the N-type epitaxial layer is 7Ω·cm, and the thickness is 18.5μm. The requirements for the vertical distribution of the resistivity of the epitaxial layer are as follows image 3 shown.

[0027] 1. Epitaxial substrate preparation: After forming a buried layer on the substrate surface through oxidation, photolithography, diffusion and other processes,...

Embodiment 2

[0033] Embodiment 2: The epitaxial equipment used in this embodiment is: PE2061S barrel type epitaxial furnace of Italian LPE Company. The specific steps of the method adopted in this embodiment are as follows: figure 1 Shown:

[0034] 1. Epitaxial substrate preparation: After forming a buried layer on the substrate surface through oxidation, photolithography, diffusion and other processes, there are often oxide layers and impurities on the substrate surface. In order to obtain a clean epitaxial substrate, the oxide layer and impurities need to be removed. Impurities. In the present invention, HF acid is used to remove the oxide layer on the surface of the buried layer substrate, and then the surface of the buried layer substrate is cleaned with silicon wafer cleaning solution SC-1 and silicon wafer cleaning solution SC-2.

[0035]2. Epitaxial vapor phase etching: Before epitaxy, in-situ HCl etching on the surface of silicon wafers is an important means to remove contaminati...

Embodiment 3

[0039] Embodiment 3: The epitaxial equipment used in this embodiment is: PE2061S barrel type epitaxial furnace of Italian LPE Company. The specific steps of the method adopted in this embodiment are as follows: figure 1 Shown:

[0040] 1. Epitaxial substrate preparation: After forming a buried layer on the substrate surface through oxidation, photolithography, diffusion and other processes, there are often oxide layers and impurities on the substrate surface. In order to obtain a clean epitaxial substrate, the oxide layer and impurities need to be removed. Impurities. In the present invention, HF acid is used to remove the oxide layer on the surface of the buried layer substrate, and then the surface of the buried layer substrate is cleaned with silicon wafer cleaning solution SC-1 and silicon wafer cleaning solution SC-2.

[0041] 2. Epitaxial vapor phase etching: Before epitaxy, in-situ HCl etching on the surface of silicon wafers is an important means to remove contaminat...

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Abstract

The invention discloses a bipolar transistor epitaxial wafer manufacturing method adopting varied temperature and varied doping flow. The bipolar transistor epitaxial wafer manufacturing method adopts the varied temperature and varied doping technologies, can effectively control evaporation of B atoms with low initial growth temperature and high N-type doping flow, and gradually suppress self-doping of an epitaxy along with the thickening of an epitaxial layer. The over-doping of N-type impurities of the epitaxial layer can be effectively reduced by reducing the doping flow subsequently, thereby guaranteeing the controllable transition region required by the product epitaxial layer, and increasing the growth temperature to suppress pattern drift.

Description

technical field [0001] The invention relates to a method for preparing bipolar transistor raw materials, in particular to a method for manufacturing bipolar transistor epitaxial wafers using variable temperature and variable doping flow. Background technique [0002] Bipolar transistors are one of the most widely used and most important semiconductor devices in integrated circuits. Bipolar transistors have a series of advantages such as low power consumption, long life, and high reliability, and have been widely used in broadcasting, television, communications, radar, computers, automatic control devices, electronic instruments, household appliances, etc., for amplification, oscillation, switching, etc. And so on. With the continuous development of semiconductor technology, on the basis of planar technology, epitaxy technology has gradually developed the manufacturing process of bipolar integrated circuits. By fabricating the N+ buried layer on the substrate, the series re...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02H01L21/8222
CPCH01L21/02367H01L21/0257H01L21/02617H01L21/8222
Inventor 仇光寅肖建农骆红金龙
Owner NANJING GUOSHENG ELECTRONICS
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