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A Thyristor Structure with Low Trigger Voltage and Low Parasitic Capacitance

A technology with parasitic capacitance and low voltage, applied in the field of thyristor structure, can solve the problems that the working voltage cannot be effectively protected and the trigger voltage is high, and achieve the effects of small parasitic capacitance, reduced turn-on voltage, and fast turn-on speed.

Inactive Publication Date: 2011-12-07
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the SCR trigger voltage is generally high, and it cannot effectively protect the working voltage of 5V and below.

Method used

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  • A Thyristor Structure with Low Trigger Voltage and Low Parasitic Capacitance
  • A Thyristor Structure with Low Trigger Voltage and Low Parasitic Capacitance
  • A Thyristor Structure with Low Trigger Voltage and Low Parasitic Capacitance

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Embodiment Construction

[0022] The present invention will be described in detail below in conjunction with the embodiments and accompanying drawings, but the present invention is not limited thereto.

[0023] Such as image 3 As shown, a thyristor structure with low trigger voltage and low parasitic capacitance includes a P-type substrate 31, and a first P-well 32, a first N-well 33, and a second P-well 34 are sequentially arranged on the P-type substrate 31 and the second N well 35, wherein the first P well 32 is closely connected to the first N well 33, the first N well 33 is closely connected to the second P well 34, and the second P well 34 is closely connected to the second N well 35 ;

[0024] Wherein, on the direction from the first P well 32 to the second N well 35, on the first P well 32, the first N well 33, the second P well 34 and the second N well 35, there are arranged in sequence: the first P+ Implantation region 36, the first N+ implantation region 38, the second N+ implantation reg...

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Abstract

The invention discloses a low-trigger-voltage and low-parasitic-capacitance silicon controlled structure which comprises a P-type substrate, wherein a first P well, a first N well, a second P well and a second N well which are tightly connected are arranged on the P-type substrate in sequence; in the direction of the first P well pointed to the second N well, a first P+ injection region positioned on the first P well, a first N+ injection region positioned on the first N well, a second N+ injection region positioned on the second P well, a third N+ injection region crossing the second P well and the second N well and a second P+ injection region on the second N well are sequentially arranged on the first P well, the first N well, the second P well and the second N well; and laminated gateoxide and a polysilicon gate are arranged between the second N+ injection region and the third N+ injection region, and shallow ditches are all partitioned between the other two adjacent injection regions. The silicon controlled structure provided by the invention can be used as an electrostatic discharge protective device for integrated circuits and has the advantages of low trigger voltage, strong robustness and low parasitic capacitance.

Description

technical field [0001] The invention belongs to the field of integrated circuits, in particular to a thyristor structure with low trigger voltage and low parasitic capacitance, which is used to improve the reliability of integrated circuit ESD protection. Background technique [0002] The phenomenon of electrostatic discharge (ESD) in nature poses a serious threat to the reliability of integrated circuits. In the industry, 30% of the failures of integrated circuit products are caused by electrostatic discharge. After entering the nanometer era of integrated circuits, the thinner gate oxide thickness greatly increases the probability of integrated circuits being damaged by electrostatic discharge. Therefore, improving the reliability of integrated circuit electrostatic discharge protection has a non-negligible effect on improving the yield of products. [0003] The modes of electrostatic discharge phenomena are usually divided into four types: HBM (Human Body Model), MM (Mac...

Claims

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Application Information

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IPC IPC(8): H01L29/74H01L29/06H01L27/02
Inventor 马飞韩雁董树荣郑剑锋苗萌吴健王洁
Owner ZHEJIANG UNIV
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