Clock network traversing testing method based on FPGA (Field Programmable Gate Array) hardware structure

Abstract

The invention belongs to the technical field of testing of integrated circuits, and specially provides a clock network traversing testing method based on the FGPA (Field Programmable Gate Array). The method is that each logic block is configured as that the SLICE in the a CLB logic block circuit (Configurable Logic Block) is configured to be in a logic gate operation form; a BRAM logic block circuit is configured to the read-only ROM address searching mode; a DSP logic block circuit is configured to be in some operation form; all configuration modes above are under the control of a clock signal, and the result is outputted through a register; the faults which can be tested include short circuit, open circuit, general 0 and 1 faults of an FPGA clock end. With the adoption of the method, the clock input ends of all unit block circuits in an FPGA chip and all clock network functions can be tested; the configuration times, configuration difficulty and the testing time for testing are greatly optimized.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a traversal test method for a clock network in an FPGA (Field Programmable Gate Array). Background technique [0002] As a semi-customized integrated circuit, FPGA not only solves the problems of long ASIC design cycle, high manufacturing cost and complex production process, but also avoids the shortcomings of the original programmable logic device gates with limited number and low operating frequency. . FPGA can be programmed through the hardware description language Verilog HDL or VHDL, the user uses the hardware description language to design the circuit, and then compiles and generates the bit stream file through the corresponding FPGA development software and downloads it to the FPGA chip, so that the FPGA chip can be quickly configured into the designed circuit. [0003] With the continuous expansion of FPGA chip scale and application fields, the t...

AI Technical Summary

Problems solved by technology

The obvious disadvantage of this method is that because the IO (input and output) ports of the FPGA are much rarer than the internal resources of the chip, more test configurations have to be used to achieve a higher fault coverage, which is undoubtedly Will greatly increase test time and test cost

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