Isolation structure of a high-voltage driving circuit and its preparation method

Abstract

The invention discloses an isolation structure of a high-voltage driving circuit and a preparation method thereof. The improvement over the traditional isolation structure lies in that one N-type well region is respectively filled on both sides of the second P-type well region, thereby improving the isolation performance. While ensuring the withstand voltage of the isolation structure, the invention suppresses the punch-through leakage between the high voltage region and the drain terminal of the lateral diffusion field effect transistor in the isolation structure.

Description

technical field [0001] The invention belongs to the field of high-voltage power integrated circuits, and in particular relates to an isolation structure of a high-voltage drive circuit and a preparation method thereof. Background technique [0002] In the field of power integrated circuits, high-voltage integrated circuits occupy an important position in the field of power integrated circuits because of their high reliability, high integration, high efficiency and low power consumption. High-voltage integrated circuits integrate high-voltage electronic devices, traditional control logic circuits and protection circuits on a single chip. It is widely used in motor controllers, electronic ballasts and automotive electronics. The level shift circuit in the high-voltage integrated circuit is a key part of the whole circuit. The leakage design of the high-voltage lateral diffusion field effect transistor (LDMOS) that constitutes the level shift circuit directly affects the norma...

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Problems solved by technology

However, when the high-voltage region is connected to high voltage, the P-type junction isolation region close to the high-voltage region can be completely depleted with the N-type well region with higher concentration on both sides, while the P-type junction isolation region far away from the high-voltage region cannot be completely depleted, resulting in partial breakdown

In view of this problem, if the doping concentration of the P-type junction isolation region is reduced, although the P-type junction isolation region can be completely depleted with the N-type well regions on both sides, the N-type well region at the high voltage region and the P-type well region will be completely depleted. The depletion layer in the junction isolation region will widen to the N-type well region inside the P-type junction isolation region, and local punch-through breakdown will occur, resulting in a decrease in the breakdown voltage of the isolation structure, resulting in leakage between the high-voltage region and the LDMOS drain

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