Design method for Cache control unit of protocol processor

Abstract

The invention provides a design method for a Cache control unit of a protocol processor. The Cache control unit of the protocol processor is used for controlling access of the protocol processor in a CC-NUMA system to caching. Full synchronization of Cache reading and writing operation time sequence and a streamline of the protocol processor is achieved by dispatching and hanging different Cache access instructions, and cache seamless access and full streamline protocol message processing are achieved under the condition that the Cache is idle and hit. A system is divided into a plurality of sub-modules according to functions and comprises a streamline instruction hanging queue, a dispatching module, a label array, a data array, a backfill module, an interface communication module and failure cache, asynchronous operation is replaced by Cache operation, and delay of Cache access caused by the asynchronous operation is removed. When the cache is hit, the protocol processing streamline can synchronously operate data in the Cache, so that efficiency for protocol processing is improved.

Description

technical field [0001] The invention relates to the fields of computer and integrated circuit design, in particular to a design method of a protocol processor Cache control unit. Background technique [0002] Cache, that is, high-speed cache, usually refers to a high-speed small-capacity memory between the processor and the main memory. The access speed is much faster than the main memory and matches the access speed of the processor. Cache is usually implemented based on static random access memory (SRAM). Compared with dynamic random access memory (DRAM), SRAM has the advantage of fast speed, but its disadvantages are high cost and large area. The Cache maps the content of a part of the main memory address with a few percent of the capacity of the main memory. When the data address accessed by the processor is just within its mapping, the processor can directly operate on the Cache, eliminating the need to access the main memory. Steps, the processing speed of the compute...

AI Technical Summary

Problems solved by technology

The disadvantage of this implementation is that the protocol processing pipeline cannot synchronously operate the data on the Cache regardless of whether the Cache is hit or not. The processing of each protocol message needs to wait for several clock cycles of Cache access time, which reduces the efficiency of protocol processing. increased system latency

Images