Chemical mechanical planarization method and manufacturing method of gate last

Abstract

The invention provides a chemical mechanical planarization method and a manufacturing method of gate last. The chemical mechanical planarization method comprises the following steps: providing a substrate with a gate as well as a source region and a drain region at two sides of the gate, wherein an isolating layer is covered on the gate as well as the source region and the drain region of the gate, and the isolating layer comprises a convex part arranged above the gate and a concave part arranged on the surface of the substrate between gates; carrying out a selective doping process on the isolating layer and only enabling the convex part to be doped; and carrying out a CMP (Chemical Mechanical Polishing) process on the doped substrate, removing the convex part and planarizing the surface of the substrate. By using the method, the isolating layer is subjected to the selective doping process and only the convex part of the isolating layer is doped, so that the chemical corrosion action of grinding liquid in the CMP process to the material of the convex part can be enhanced, the removal rate of the material of the convex part in the CMP process is increased, the uniformity in a chip in a grinding process is improved, furthermore, no residual metal exists in the isolating layer between the gates in the forming process of the gate last, and a short circuit defect of a device can be avoided.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a chemical mechanical planarization method. Background technique [0002] With the increasing demand for high integration and high performance of VLSI, semiconductor technology is developing towards technology nodes with feature sizes of 45 nanometers or even smaller. Due to the successful application of the high-K / metal gate process on the 45nm technology node, this process has become an indispensable key process module for the technology node below 30nm. At present, in terms of mass production of 45nm and 32nm chips, only Intel, which adheres to the high-K / gate last process, has achieved success. In recent years, Samsung, TSMC, Infineon, etc. Industry giants will also shift their development focus from high-K / gate first to gate last. [0003] For the gate last process, the development of the chemical mechanical planarization (CMP) process is considere...

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Problems solved by technology

[0005] However, the problem is that due to the high density of the polysilicon gate 11, and the gate height difference exists on the substrate surface before the deposition of the silicon oxide spacer 13, which is about 1000A to 1800A, the polysilicon gate 11 after the silicon oxide spacer 13 is deposited The thickness difference h of the silicon oxide isolation layer 13 between the top and the source and drain regions (not shown in the figure) can reach 1000A to 4000A, or even more

The conventional silicon oxide CMP process usually cannot effectively eliminate such a large thickness drop, and it will be inherited until the grinding process of the silicon oxide isolation layer 13 is completed as the grinding process progresses, such as figure 2 As shown, this drop causes pits 14 to be formed in the remaining silicon oxide isolation layer 13 between the polysilicon gates 11, and it is difficult to repair even the CMP of the silicon nitride isolation layer 12 in the next step. It is possible to further enlarge the pit 14 of this silicon oxide isolation layer 13

like image 3 and Figure 4 As shown, the pits 14 of the silicon oxide isolation layer are also filled with metal materials, which will directly cause huge obstacles to the process in the subsequent metal gate CMP process, greatly compress the adjustment space of the process, and easily cause gaps between the gates. Metal residues, causing short circuits in the device

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