Method for manufacturing groove type longitudinal semiconductor device

Abstract

The invention discloses a method for manufacturing a groove type longitudinal semiconductor device, belonging to the technical field of manufacture of semiconductor devices. In the invention, the process manufacturing of the groove type longitudinal semiconductor device can be realized through the process steps such as deep groove etching, high-temperature diffusion, insulating medium padding andplanarization, active layer and electrode forming and the like. Compared with the existing process, the process method disclosed by the invention has the following advantages: firstly, a narrow and high-concentration P column region or N column region (namely a second semiconductor drift region) are be formed, thereby being beneficial to reduction of on resistance and decrease of horizontal dimension of the device; secondly, the bottom of a groove grid is ensured to be parallel to the lower interface of a body region or be slightly lower than the lower interface of the body region, further improving the withstand voltage of the device and reducing the low-grid and grid-drain capacitance; and thirdly, complicated masking is not required, and the influence of small-angle injection to the channel region can be avoided; and fourthly, the negative influence on the formed body region, body contact region and source region caused by the padding and planarization of the extended groove as well as manufacturing and planarization of the groove grid can be avoided.

Description

technical field [0001] The invention belongs to the technical field of semiconductor device manufacturing, and in particular relates to a method for manufacturing a semiconductor device with deep grooves. Background technique [0002] Power MOSFET is a multi-subconduction device, which has many advantages such as high input impedance, high frequency, and positive temperature coefficient of on-resistance. These advantages make it widely used in the field of power electronics, greatly improving the efficiency of electronic systems. [0003] The high voltage resistance of the device requires a long drift region and a low doping concentration in the drift region. However, as the length of the drift region increases and the doping concentration decreases, the on-resistance (R on ) increases, the on-state power consumption increases, and the device on-resistance R on There is the following relationship with the breakdown voltage BV: that is, R on ∝BV 2.5 . [0004] With the ...

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Problems solved by technology

However, after forming the active region (including the body region 5, the body contact region 7 and the source region 9), the process steps of small-tilt-angle ion implantation, oxide-filled extension trenches, and trench gate formation have the following main disadvantages: (1 ) process is difficult to accurately control the height of silicon dioxide in the first trench

On the one hand, the groove gate must span the body region in the vertical direction (that is, the upper surface of the oxide in the first trench cannot be higher than the lower surface of the body region); on the other hand, the longer the groove shed overlaps with the drift region, the gate-drain The greater the capacitance, and the withstand voltage of the device decreases with the decrease of the height of silicon dioxide in the first trench, so the height of silicon dioxide in the first trench needs to be accurately controlled in the process to ensure the electrical performance of the device; (2) the device The higher the withstand voltage, the deeper the first trench, the more difficult the implantation, and the smaller the process tolerance; (3) In order to ensure that the ions implanted at a small inclination angle cover all areas below the active layer on both side walls of the trench, and do not cover the trench Active layer on both side walls, mask for ion implantation ( image 3 13 is the mask) is more difficult to do, increasing the complexity of the process

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