LDMOS device manufacturing method, LDMOS device and terminal equipment

Abstract

The invention discloses an LDMOS device manufacturing method. The method comprises the following steps: forming shallow trench isolation and a gate dielectric layer on a substrate or an epitaxial layer, and defining a polysilicon gate; forming a high-energy drift region, an RESUR layer injection region and a low-energy drift region; photoetching the polysilicon gate, reserving photoresist after etching, and performing injection to form a body region; forming a side wall, forming a first heavily doped region and a second heavily doped region in the body region, forming a first heavily doped region in the low-energy drift region, and depositing a metal silicification reaction barrier dielectric layer; forming metal silicide on the surfaces of the polysilicon gate, the first heavily doped region and the second heavily doped region; depositing an insulating medium etching stop layer, and depositing an interlayer dielectric layer; and forming a plurality of contact holes and a first metal layer, short-circuiting a first part of contact holes close to one side of a channel to the grid electrode through the metal layer, and short-circuiting a second part of contact holes close to one side of a drain electrode to a source electrode. The invention further discloses an LDMOS device and terminal equipment used for manufacturing the LDMOS device.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing an LDMOS device, an LDMOS device and a terminal device for manufacturing the LDMOS device. Background technique [0002] DMOS (Double-diffused MOS) is currently widely used in power management circuits due to its characteristics of high voltage resistance, high current drive capability and extremely low power consumption. In LDMOS (Lateral Double-diffused MOS) devices, on-resistance Rsp and gate-drain capacitance Cgd are two important indicators of LDMOS devices. How to obtain higher breakdown voltage, lower Rsp, and lower Cgd can improve the competitiveness of products. [0003] Existing LDMOS structures such as figure 1 As shown, the field plate for adjusting the electric field is formed by introducing conductive contact holes on the dielectric layer SAB, but in the traditional structure, 116-A is either directly shorted to the gate or dir...

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Problems solved by technology

[0003] Existing LDMOS structures such as figure 1 As shown, the field plate for adjusting the electric field is formed by introducing a conductive contact hole on the dielectric layer SAB, but in the traditional structure, 116-A is either directly shorted to the gate or directly shorted to the source

In the on state, the contact hole is shorted to the gate to form an additional electron accumulation layer above the drift region to reduce Rsp, but the gate-drain capacitance is large, and the contact hole is shorted to the source to shield the gate. Reduce gate-drain capacitance, but cannot create an electron accumulation layer, thus increasing Rsp

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