Micro-architecture sensitive thread scheduling (MSTS) method

Abstract

The invention relates to a micro-architecture sensitive thread scheduling (MSTS) method. The method comprises two-level scheduling strategies: in the inner portions of nodes, according to the structural characteristics of CMP, through acquiring relevant information of cache invalidation in real time, the threads which excessively compete for the shared cache resources operate in a staggered mode in time and spatial dimension, and the threads which can carry out effective mutual data sharing operate simultaneously or successively; and in a layer between nodes, through sampling memory data areas frequently accessed by the threads, the threads are bound to the nodes in which data are arranged as far as possible so as to reduce the access to a remote memory and reduce the amount of communication between chips. The method provided by the invention has the advantages of reducing the access delay caused by simultaneously operating a plurality of threads with large shared cache contention, and improving the operation speeds and system throughput rates of the threads.

Description

technical field [0001] The invention mainly relates to the field of thread scheduling design in the operating system, in particular to the thread scheduling design in shared Cache on-chip multi-core processor (CMP) nodes and among distributed shared storage structure system nodes composed of multiple slices. In particular, it refers to an operating system thread scheduling method that is aware of microarchitecture information. Background technique [0002] The current multi-core processor technology alleviates the contradiction between the rapid growth of processor performance and the slow growth of memory performance to a certain extent, but the storage speed of memory is still a key factor restricting the improvement of processor performance. Modern computer systems implement functions such as out-of-order execution, multi-instruction launch, and loop unrolling through hardware, which greatly hides processor memory access delays. At the operating system level, the priorit...

AI Technical Summary

Problems solved by technology

Considering that the thread scheduling algorithm must be simple and efficient, it is often difficult to analyze the cache failure rate and memory access address without hardware support.

Modern processors generally provide PMU, which is a set of counters that can count the underlying events of the processor. Although the counters of most processors are architecture-related and do not provide users with a unified interface, most of them can provide The statistics of basic information such as Cache failure rate and memory access address analysis, how to make full use of PMU to perceive the underlying information in real time and provide guidance for the operating system to schedule (thread) threads has attracted more and more attention from the academic community.

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