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Integrated circuit structure

By arranging the internal connection points outside the metal oxide semiconductor area in the integrated circuit, and using generally straight gate electrode wires and vertically overlapping power supply wires, the line width uniformity and third problems caused by the distortion of polysilicon wires in the integrated circuit are solved. The utilization rate of the second metallization layer improves layout efficiency and flexibility.

Active Publication Date: 2009-12-30
TAIWAN SEMICON MFG CO LTD
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  • Abstract
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  • Claims
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Problems solved by technology

However, the above methods (such as the polysilicon protrusion method) either violated other design specifications or caused an undesired increase in the utilization of the second metallization layer

Method used

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Embodiment Construction

[0073] The present invention provides a novel layout method of standard cells and its final layout situation. And discuss the differences through different embodiments. In the case of illustration in different figures of the present invention, the same reference numerals represent the same elements. In the following, descriptions such as "horizontal" and "horizontally" indicate that the circuit of the present invention is arranged in a direction parallel to the surface of the chip, while descriptions such as "vertical" and "vertically" indicate that it is perpendicular to the surface of the chip. The orientation of the surface.

[0074] figure 2 An embodiment according to the invention is shown, in which a part of cell C1 is shown. Cell C1 may be stored in a cell library, an I / O cell, an embedded cell, a Dynamic Random Access Memory (DRAM) cell, a Static Random Access Memory (SRAM) cell, a hybrid Part of a standard unit of a signal circuit unit or the like. The border of...

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Abstract

The invention discloses an integrated circuit structure, comprising a p-type metal oxide semiconductor transistor having a first gate electrode, a first source electrode and a first drain electrode; and an n-type metal oxide semiconductor transistor having a second source electrode, a second drain electrode and a second gate electrode, wherein the second gate electrode and the first gate electrode are a part of a grate electrode lead. Other transistors are not arranged between the p-type metal oxide semiconductor transistor and the n-type metal oxide semiconductor transistor. The integrated circuit structure further comprises a power lead connected with the first source electrode; a grounding lead connected with the second source electrode; and an inside connection point electrically connected with the grate electrode lead. The inside connection point is located outside a region of metal oxide semiconductor comprising the region of a PMOS transistor, an NMOS transistor and between the two ones, wherein the grate electrode lead is located at the region straightly in general. The invention can improve the line width uniformity of the grate electrode lead.

Description

technical field [0001] The present invention relates to integrated circuits, and more particularly to optimization of the layout of integrated circuits. Background technique [0002] As the dimensions of integrated circuits continue to shrink, integrated circuit devices become more integrated, and many restrictive design rules apply, the main limitation of which is layout design. For standard cells commonly used in integrated circuits, these restrictive design specifications have resulted in an increase in the area used by the chip, increased difficulty in auto placement and routing, and violations of design specification inspections. and so on. [0003] Usually in order to comply with restrictive design specifications, the following methods can be used, including increasing the area of ​​the unit to avoid violations of design specifications, using more metal routing to minimize violations of design specifications, and increasing the utilization rate in the chip area To so...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/092H01L23/528H01L29/78H01L29/423
CPCH01L27/0207H01L27/092H10D89/10H10D84/85
Inventor 田丽钧鲁立忠侯永清戴春晖郭大鹏陈胜兴李秉中
Owner TAIWAN SEMICON MFG CO LTD
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