Array substrate, manufacturing method thereof, and display device
The technology of an array substrate and a manufacturing method, which is applied in the field of array substrate manufacturing, can solve the problem of increasing the coupling capacitance between the data line 4 and the common electrode line, adverse effects, increasing the coupling capacitance between the data line and the common electrode line or the data line and the scanning line, etc. question
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0073] Such as image 3 As shown, the array substrate according to one embodiment of the present invention includes:
[0074] base1;
[0075] Gate lines 5, common electrode lines 3 and data lines 4 arranged on the substrate;
[0076] The first spacer layer 10 disposed in the first overlapping area of the common electrode line 3 and the data line 4 and located between the common electrode line 3 and the data line 4, the first spacer layer 10 extends at least in the width direction of the data line 4 One side is extended to a preset length;
[0077] and / or
[0078] The second spacer layer 20 arranged in the second overlapping area of the gate line 5 and the data line 4, and between the gate line and the data line 4, the second spacer layer 20 in the second overlapping area is in the width direction of the data line 4 The top extends to at least one side for a preset length.
[0079] The first spacer layer 10 can increase the distance between the common electrode line ...
Embodiment 2
[0091] Such as Figure 7 As shown, preferably, according to yet another embodiment of the present invention, the array substrate further includes:
[0092] a gate 2 disposed on the substrate 1,
[0093] The second spacer layer 20 is also arranged in the third overlapping area between the gate 2 and the data line 4, and is located between the gate 2 and the data line 4,
[0094] The second spacer layer 20 in the third overlapping region extends to at least one side in the width direction of the data line 4 by a predetermined length.
[0095] Compare Figure 7 with image 3 It can be seen that there is an overlapping area between the gate 2 and the data line 4 in the second embodiment, which is intuitively expressed as Figure 7 The gate 2 in the ratio image 3 The gate 2 is large, not only located under the active layer 6, but also located under the data line 4, the specific cross-sectional view is as follows Figure 9 shown.
[0096] Since multiple pixel areas in the ar...
PUM
Abstract
Description
Claims
Application Information
- R&D Engineer
- R&D Manager
- IP Professional
- Industry Leading Data Capabilities
- Powerful AI technology
- Patent DNA Extraction
Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.
© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com