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Semiconductor device and manufacturing method thereof

A technology of semiconductors and devices, applied in the field of manufacturing semiconductor devices with field effect transistors

Inactive Publication Date: 2007-11-21
RENESAS TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] On the other hand, the size of the MISFET is smaller, so that the gate resistance increases due to the reduction of the gate length, and the source region resistance, drain region resistance and contact resistance increase due to the shallower source region and drain region. Barriers to Improvement of Memory ICs (Integrated Circuits), Logic ICs, and Hybrid ICs with Memory and Logic Functions

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

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Embodiment approach 1

[0161] Embodiment Mode 1 describes an example in which the present invention is applied to a semiconductor device having complementary MISFETs.

[0162] FIG. 1 is a cross-sectional view showing a schematic structure of a complementary MISFET incorporated in a semiconductor device of Embodiment 1. Referring to FIG. In FIG. 1, an n-type MISFET is shown on the left, and a p-type MISFET is shown on the right.

[0163] As shown in FIG. 1 , the semiconductor device of Embodiment Mode 1 mainly includes, as a semiconductor substrate (silicon layer as a semiconductor substrate) 1 , for example, a p-type single crystal silicon substrate.

[0164] Device fabrication regions 1n and 1p are arranged on the main surface (device fabrication surface or circuit fabrication surface) of the silicon substrate 1, which are isolated from each other by the device isolation region 2, and a p-type well region 4 and an n-type well region 4 are formed in the device fabrication region 1n. MISFET, and an ...

Embodiment approach 2

[0227] 22 to 24 are schematic cross-sectional views illustrating the manufacturing steps of the semiconductor device according to Embodiment 2 of the present invention.

[0228] In Embodiment Mode 2, it is described that the condensation of the refractory metal is suppressed during silicidation.

[0229] After the contact regions (semiconductor regions 12, 13) of the n-type and p-type MISFETs are fabricated using the same process as that of the first embodiment, as shown in FIG. and 1p internal ion implantation of group IV elements, eg, Ge, as shown in Figure 23. By the ion implantation of Ge, Ge is introduced into the contact region in addition to the Ge ions implanted before the step of forming the extension region.

[0230] Then, heat treatment is used to activate the impurity (As, BF 2 ). The heat treatment was performed under the same conditions as in Embodiment 1 above.

[0231] In this step, since the Ge ions implanted in the step of making the extension region and ...

Embodiment approach 3

[0238] In this embodiment mode, an example of applying the present invention to a semiconductor device having complementary MISFETs and DRAM (Dynamic Random Access Memory) type memory cells on the same substrate is described.

[0239] Fig. 25 shows the schematic structure of the semiconductor device of Embodiment 3 (Fig. 25(a) is a schematic cross-sectional view of a complementary MISFET, and Fig. 25(b) is a schematic cross-sectional view of a memory cell selecting a MISFET), and Fig. 26 is a schematic cross-sectional view of a memory cell installed in the implementation mode. An equivalent circuit diagram of a memory cell in the semiconductor device of Embodiment 3. FIG. 27 is a schematic cross-sectional view showing the manufacturing steps of the semiconductor device of Embodiment 3. FIG. In 25(a), the device fabrication region 1n on the left is an n-type MISFET, and the device fabrication region 1p on the right is a p-type MISFET.

[0240] As shown in FIG. 26, memory cells ...

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Abstract

A method of manufacturing a semiconductor device having a field effect transistor with improved current driving performance (increase of drain current) of a field effect transistor comprising the steps of ion implanting a group IV element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode.

Description

[0001] This application is a divisional application of the patent application with the application number 200310122393.5, the application date is December 19, 2003, and the invention title is "semiconductor device and its manufacturing method". technical field [0002] The present invention relates to semiconductor devices and fabrication methods thereof, and more particularly to an effective technique for fabricating semiconductor devices having field effect transistors. Background technique [0003] As field effect transistors incorporated in semiconductor devices, for example, insulated gate field effect transistors called MISFETs (Metal-Insulator-Semiconductor Field Effect Transistors) are well known. Since MISFET is suitable for high-integration use, it has generally been used as a transistor to form an integrated circuit. [0004] A general structure of a MISFET includes a channel formation region, a gate insulating film, a gate electrode, a source region, and a drain ...

Claims

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Application Information

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IPC IPC(8): H01L21/8238H01L21/336H01L21/822H01L21/265H01L21/324H01L21/306
Inventor 满田胜弘本多光晴饭塚朗
Owner RENESAS TECH CORP
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