LDO circuit using bidirectional asymmetry buffer structure to improve performance

Abstract

An LDO circuit that uses a bidirectional asymmetric buffer structure to improve performance. A bidirectional asymmetric buffer structure is used to provide a feedback path with a signal reverse function and a forward path with a signal same direction function. The feedback path is used to realize the frequency of the LDO circuit. To compensate and improve the transient response performance, the forward path is used to offset the right half-plane zero point generated by the gate-drain parasitic capacitance of the LDO transmission element, thereby improving the stability of the system and expanding the unity gain bandwidth. The circuit has the advantages of simple structure, low power consumption, and can effectively eliminate the zero point of the right half plane.

Description

Technical field [0001] The invention relates to an LDO circuit, in particular to an LDO circuit that uses a bidirectional asymmetric buffer structure to effectively eliminate the right half-plane zero in a low dropout linear regulator, thereby enhancing loop stability and improving system performance. Background technique [0002] A closed-loop negative feedback system is usually used in linear circuits. For example, in a Low-Dropout Voltage Regulator (LDO), a feedback loop is used to obtain a stable output voltage. In order to reduce the input and output voltage difference (Dropout voltage) and enhance the current drive capability, the transmission element in the LDO (also called transmission tube, pass tube, power tube, Pass Element, Power Device, etc.) usually has a great aspect ratio ( Such as 20000μm / 1μm), so its gate-drain parasitic capacitance C gd Usually larger (such as 10pF). Parasitic capacitance C gd And the transconductance g of the transmission element mp Form a fre...

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Problems solved by technology

Therefore, this circuit does not eliminate the right-half-plane zero ω ZRHP

In addition, the circuit also has the following disadvantages: the capacitive load driving ability is weak, and a large compensation capacitor C is required f , thereby increasing the chip area, reducing the slew rate and transient response speed of internal nodes; reducing the power supply rejection ratio (Power Supply Rejection Ratio, PSRR) performance of the LDO

However, this right-half-plane zero cancellation mechanism based on the forward transconductance stage has the following disadvantages: First, the forward transconductance stage can only provide the forward path, so the feedback compensation mechanism cannot be realized

For this reason, it is necessary to add an additional feedback compensation circuit, which increases the complexity of the circuit and may lead to a reduction in response speed and PSRR performance; secondly, the forward transconductance stage 301 increases the complexity of the circuit and introduces an additional offset voltage, and increases the parasitic capacitance at the input of the gain stage 101; more importantly, the forward transconductance stage is suitable for applications where the output stage is a Push-Pull or Class-AB structure

In the LDO circuit, the output stage is a transmission element, so the introduction of the forward transconductance stage increases the quiescent current of the LDO, which is not conducive to low power consumption design

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