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Construction method of non-regular permutation matrix LDPC code and its device

A technology of LDPC code and permutation matrix, applied in the field of information, can solve the problems of increasing the complexity of decoder implementation, destroying the block structure of H matrix, etc.

Inactive Publication Date: 2008-11-26
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

First, in terms of performance, most of the current permutation matrix LDPC codes are worse than PEG-LDPC codes, which brings great uncertainty to the application of permutation identity matrix LDPC codes; Using systematic codes, the traditional permutation unit matrix LDPC systematic codes adopt the form of adjacent double diagonals. This form of systematic codes destroys the block structure of the entire H matrix. Although it provides convenience for encoding and decoding, it also improves translation. Encoder Implementation Complexity

Method used

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  • Construction method of non-regular permutation matrix LDPC code and its device
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  • Construction method of non-regular permutation matrix LDPC code and its device

Examples

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Embodiment 1

[0080] Embodiment 1: Constructing an irregular permutation matrix LDPC code

[0081] The following specifically describes the process of constructing a (1008,504) LDPC system code by using the construction method described in the present invention:

[0082] Step 1, determine the parameters of the H matrix. Given that the code length N=1008 and the number of check equations M=504, the size of the H matrix is ​​504×1008. Calculate the factors of M and N separately, we can get N=28×36, M=14×36, so we can choose the size of each sub-block to be 36×36, and the whole matrix can be divided into 14×28 sub-blocks ;

[0083] Step 2, using the density deduction method to determine the dimensional distribution of the H matrix. Determine the dimension distribution function of the variable node as λ(x)=0.2947x+0.2842x 2 +0.4211x 7 , that is, the edges connected by variable nodes with a dimension of 2 account for 29.47% of the total number of edges, the edges connected by variable nodes...

Embodiment 2

[0096] Example 2: Encoder

[0097] The hardware structure of the encoder is as follows Figure 18As shown, the encoder includes information bit input (DUPLICATE), information bit buffer RAM, partial checksum RAM (RAM#1_1...), partial checksum update (XOR#1...), interleaving, node bit buffer RAM , a row interleaving index ROM, an accumulation interleaver, a parity bit buffer RAM, a column interleaving index ROM and a codeword bit output (MUX) module. Among them, the information bit input (DUPLICATE) copies the input information bits into two parts, which are respectively input into the information bit buffer RAM and part of the checksum update module. The information bit buffer RAM includes three memory RAMs, each of which has a size of 504 bits. The three memory RAMs cyclically store the input information bits, and output them at the end of the encoding, which plays a role in delaying the information bits. The partial checksum RAM includes a 504-bit memory, which is used to ...

Embodiment 3

[0098] Embodiment 3: Decoder

[0099] The overall structure of the decoder is as follows Figure 15 As shown, it can be divided into four parts: Controller (control module), Memory (memory), VNU (variable node computing unit) and CNU (check node computing unit).

[0100] Among them, a total of 28 variable node calculation units are required, and a total of 14 check node calculation units are required. The decoding algorithm can use a simplified algorithm of the sum-product algorithm—the minimum sum algorithm. Since there are 94 non-zero permutation matrices in the constructed H matrix, a total of 188 dual-port RAMs with a size of 36×7 bits (here, the quantization width is taken as 7) are required to provide decoding for two codewords at the same time, and they are used as storage units For simultaneous decoding of two codewords, intermediate data is provided to the variable node computing unit and the check node computing unit for calculation.

[0101] Such as Figure 21 As...

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Abstract

This invention relates to a method for constructing new non-standard replacement matrix LDPC codes characterizing that under the principle of optimizing the smallest ring circuit, it takes each sub-block as the smallest unit and utilizes a binary chart with weight to determine the position of the sub-block and the deviation of circulation shift: simplifying the binary chart with bit as the unit of the LDPC code to that with a sub-block as the unit based on the property of the matrix of a replacement unit, then applying the traditional PEG algorithm with the bit as the unit to the new chart with the sub-block as the unit to determine the position of every replacement unit matrix of the H matrix and finally utilizing the ring circuit property of the LDPC code to decide the deviation of circular shift of each replacement unit matrix.

Description

technical field [0001] The invention relates to a channel coding technology, in particular to a method for constructing an irregular permutation matrix LDPC code with the maximum minimum cycle, and belongs to the field of information technology. Background technique [0002] Channel coding technology, as the basic technology to ensure the reliable transmission of communication system, has been developed rapidly in the past ten years. A large number of channel codings represented by Turbo code and LDPC code (low density parity check code) can approach the theoretical limit one after another. It has been discovered and studied deeply, among which LDPC code has received special attention in recent years. In the formulation of various communication standards, it is widely considered to be able to replace Turbo code and become the main channel coding scheme of the next generation communication system. [0003] As a linear block code, the LDPC code must satisfy the following three...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/00H03M13/11
Inventor 乔华管武董明科金野梁庆林项海格
Owner PEKING UNIV
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