Power and signal line bussing method for memory devices

Abstract

A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to a power and signal line bussing method for high density and high speed memory devices.2. Description of the Prior ArtA conventional power line bussing method is shown in FIG. 1. Chip 1 has two memory cell arrays 2 centered around peripheral circuitry 4, which comprises multiple logic circuits. Power line 3a supplies power from Vcc pad to peripheral circuitry 4. Power line 3a runs from Vcc pad 5, around memory cell array 2, to peripheral circuitry 4. Ground line 3b electrically connects peripheral circuitry 4 with GND pad 5'. Ground line 3b runs from GND pad 5', around memory cell array 2, to peripheral circuitry 4.However, employing a single power line 3a to couple power to peripheral circuitry 4 does not effectively reduce noise. To best reduce noise, a power line should be coupled independently to each circuit in peripheral circuitry 4. Yet, separating power line 3a further would increase the chip...

AI Technical Summary

Benefits of technology

Another object of the present invention is to reduce chip noise generated in high speed memory devices without increasing chip size.

Still another object of the present invention is to provide a fast access time by eliminating excess path distance.

Yet another object is to provide an additional insulative layer above memory cells to reduce soft error.

Problems solved by technology

However, employing a single power line 3a to couple power to peripheral circuitry 4 does not effectively reduce noise.

However, signal line bussing according to this arrangement results in large signal delays because signals from pad 6 or internal circuit 6' must propagate the extra distance required to circumvent memory cell arrays 2.

A final disadvantage of conventional bussing arrangement arises inherently from the design.

Yet, even with the passivation and insulation layers, radiation generated from the package material layer penetrates the memory cells and causes a soft (or operation) error.

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