Three-dimensional chip-stack package and active component on a substrate

Abstract

The 3D chip-stack package comprises a component-embedded plate and a side IC. The PCB has a plurality of conductive contacts. The component-embedded plate comprises a dielectric layer; an active component embedded in the dielectric layer, one surface of each active component exposed outside the dielectric layer, the active components having a plurality of TSVs (Through Silicon Via), one ends of the TSVs exposed outside the exposed surface, the other ends of the TSVs corresponding to the conductive contacts of the PCB; and an electrical circuit on the dielectric layer and in electrical connection between the other ends of the TSVs of the active component and the corresponding conductive contacts of the PCB, respectively. The side IC has a plurality of pads. The pads are electrically connected with the exposed ends of the TSVs of the active component.

Description

[0001]The present application is a continuation-in-part of parent application Ser. No. 11 / 252,572, filed Oct. 19, 2005, which claims the benefit of Taiwan Patent Application No. 093135743, filed on Nov. 19, 2004. The parent application and the Taiwan application are hereby incorporated by reference for all purposes as if fully set forth herein.BACKGROUND[0002]1. Field of Invention[0003]The invention relates to a three-dimensional (3D) chip-stack package structure. In particular, it relates to a structure of embedded active components having TSVs (through silicon via).[0004]2. Related Art[0005]In order to create larger space and to enhance the functions of the module within a limited substrate area, shrunk or embedded passive components are often used to minimize the circuit layout and to reduce the signal transmission distance. Thus, more space is left for installing active components and enhancing the overall performance. Therefore, substrates with passive components such as embedd...

AI Technical Summary

Benefits of technology

[0011]In view of the foregoing, an objective of the invention is to provide 3D chip-stack package adapted to be disposed on a PCB with less thermo stress therebetween. The thermo stress problem in subsequence can be solved.

[0013]The pitches between the TSVs of the active component are smaller than the pitches between the conductive contacts of the PCB. Therefore, the 3D chip-stack package achieves the results of re-distribution (fan-out) of bonding pads of stacked ICs and less thermo stress between the PCB and stacked IC.

Problems solved by technology

It is likely to damage other components not to be embedded.

The finished substrate is not flexible and has limited applications.

'050 re-distributes the bonding pads by several stacked ICs, the bonding strength is not good enough.

In other words, CT of the chip mismatches that of the PCB.

This will cause cracks and bad electrical connections.

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