Controlling method for gate formation of semiconductor device

Abstract

A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes. The invention provides a simple and economic method and system of controlling gate formation of semiconductor devices. The method control the gate, as well as not leading to a notable decrease in production.

Description

technical field [0001] The present invention relates to the manufacturing process of semiconductor devices, in particular to the gate formation control of semiconductor devices. Background technique [0002] Current demands for high density and high performance in ultra-scale integrated circuits require sub-micron components, increased transistor and circuit speed, and improved reliability. These demands require the formation of device elements with high precision and consistency. While these device elements are still in the form of semiconductor wafers, then careful process monitoring is required, including device frequency and detailed inspection. [0003] When the design rules shrink and the process window (such as the limit of error in the process) becomes smaller, the inspection and determination of the critical dimension (Critical Dimension, CD) of the surface element and its cross-sectional shape (profile) become more and more important . Wherein, the critical dime...

AI Technical Summary

Problems solved by technology

[0005] Although equipment can be used to determine the critical dimension and profile of the gate of the device, this device generally cannot provide immediate response to the photolithography process to reduce variation, and the traditional inspection results are generally not used to adjust the subsequent etching process

In addition, due to process variations, gate critical dimensions and profile will be affected by factors unknown to the designer, making it difficult to obtain a complete set of process control

Images